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data sheet, v1.2, march 2006 microcontrollers xc167ci-16f 16-bit single-chip microcontroller with c166sv2 core
edition 2006-03 published by infineon technologies ag 81726 mnchen, germany ? infineon technologies ag 2006. all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hints give n herein, any typical values stated herein and/or any information regarding the application of the devi ce, infineon technologies hereby disclaims any and all warranties and liabilities of an y kind, including without lim itation warranties of non- infringement of intellectual property rights of any third party. information for further information on technology, delivery terms an d conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or system s with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
data sheet, v1.2, march 2006 microcontrollers xc167ci-16f 16-bit single-chip microcontroller with c166sv2 core
xc167-16 derivatives data sheet v1.2, 2006-03 xc167 revision history: v1.2, 2006-03 previous version(s): v1.1, 2003-06 v1.0, 2002-10 page subjects (major chan ges since last revision) all layout of graphics and text stru ctures has been ada pted to the new company documentation rules. 73 minimum oscillator period corrected 77 output delay/hold time of a23 ? a16 moved from tc 11 -> tc 12 , tc 21 -> tc 23 82 parameter tc 40 corrected 85 chapter ?package a nd reliability? added. we listen to your comments any information within this do cument that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to th is document) to: mcdocu.comments@infineon.com
xc167-16 derivatives table of contents data sheet 3 v1.2, 2006-03 1 summary of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 general device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 pin configuration and definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 memory subsystem and organiza tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 external bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 central processing unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.5 on-chip debug support (ocds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.6 capture/compare units (capcom 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.7 the capture/compare unit capc om6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.8 general purpose timer (gpt12e) unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.9 real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.10 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.11 asynchronous/synchronous serial interfaces (asc0/asc1) . . . . . . . . . . 45 3.12 high speed synchronous seri al channels (ssc0/ssc1) . . . . . . . . . . . . 46 3.13 twincan module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.14 iic bus module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.15 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.16 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.17 parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.18 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.19 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.1 general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.2 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3 analog/digital converter parame ters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.4 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.4.1 definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.4.2 on-chip flash operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.4.3 external clock drive xtal1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.4.4 testing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.4.5 external bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5 package and reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.1 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.2 flash memory parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table of contents
xc167 16-bit single-chip microc ontroller with c166sv2 core xc166 family data sheet 4 v1.2, 2006-03 1 summary of features ? high performance 16-bit cpu with 5-stage pipeline ? 25 ns instruction cycle time at 40 mhz cpu clock (singl e-cycle execution) ? 1-cycle multiplication (16 16 bit), background division (32 / 16 bit) in 21 cycles ? 1-cycle multiply-and-accumu late (mac) instructions ? enhanced boolean bit manipulation facilities ? zero-cycle jump execution ? additional instructions to su pport hll and operating systems ? register-based design with mult iple variable register banks ? fast context switching support with two additional loca l register banks ? 16 mbytes total linear addr ess space for code and data ? 1024 bytes on-chip special function re gister area (c166 family compatible) ? 16-priority-level interrupt system with 77 sources, sample-rate down to 50 ns ? 8-channel interrupt -driven single-cycle data transfer facilities via peripheral event controller (pec), 24-bit pointers cover total address space ? clock generation via on-chip pll (factors 1:0.15 ? 1:10), or via prescaler (factors 1:1 ? 60:1) ? on-chip memory modules ? 2 kbytes on-chip dual-port ram (dpram) ? 4 kbytes on-chip data sram (dsram) ? 2 kbytes on-chip progr am/data sram (psram) ? 128 kbytes on-chip progra m memory (flash memory) ? on-chip peripheral modules ? 16-channel a/d converter wi th programmable resolution (10-bit or 8-bit) and conversion time (down to 2.55 s or 2.15 s) ? two 16-channel ge neral purpose capture/compare units (32 input/output pins) ? capture/compare unit fo r flexible pwm signal generation (capcom6) (3/6 capture/compare channe ls and 1 compare channel) ? multi-functional general pur pose timer unit with 5 timers ? two synchronous/asynchronous serial channels (usarts) ? two high-speed-synchr onous serial channels ? on-chip twincan interface (rev. 2. 0b active) with 32 message objects (full can/basic can) on two can nodes, and gatewa y functionality ? iic bus interface (10-bit addressing, 400 kbit/s) with 3 channels (multiplexed) ? on-chip real time clock, dr iven by dedicated oscillator ? idle, sleep, and power down mode s with flexible power management ? programmable watchdog time r and oscillator watchdog
xc167-16 derivatives summary of features data sheet 5 v1.2, 2006-03 ? up to 12 mbytes external address space fo r code and data ? programmable external bus characte ristics for differ ent address ranges ? multiplexed or demultiplexed external address/data buses ? selectable address bus width ? 16-bit or 8-bit data bus width ? five programmable ch ip-select signals ? hold- and hold-acknowledg e bus arbitration support ? up to 103 general purpose i/o lines, partly with selectable input thresholds and hysteresis ? on-chip bootstrap loader ? supported by a large range of deve lopment tools like c-compilers, macro-assembler packages, emulators, evaluation boards, hll-debuggers, simulators, logic an alyzer disassemblers, programming boards ? on-chip debug support via jtag interface ? 144-pin tqfp package, 0. 5 mm (19.7 mil) pitch ordering information the ordering code for infineon microcontrol lers provides an exact reference to the required product. this or dering code identifies: ? the derivative itself, i.e. it s function set, the temperature range, and the supply voltage ? the package and the type of delivery. for the available ordering codes fo r the xc167 please refer to the ?product catalog microcontrollers? , which summarizes all available microcontroller variants. note: the ordering codes for mask-rom vers ions are defined fo r each product after verification of the respective rom code. this document describes several derivatives of the xc167 group. table 1 enumerates these derivatives and summarizes the differences . as this document re fers to all of these derivatives, some descriptions may not apply to a sp ecific product. for simplicity all versions are referred to by the term xc167 throughout th is document.
xc167-16 derivatives summary of features data sheet 6 v1.2, 2006-03 table 1 xc167 derivative synopsis derivative 1) 1) this data sheet is valid for devices st arting with and including design step ad. temp. range program memory on-chip ram interfaces SAK-XC167CI-16F40F, sak-xc167ci-16f20f -40 c to 125 c 128 kbytes flash 2 kbytes dpram, 4 kbytes dsram, 2 kbytes psram asc0, asc1, ssc0, ssc1, can0, can1, iic saf-xc167ci-16f40f, saf-xc167ci-16f20f -40 c to 85 c 128 kbytes flash 2 kbytes dpram, 4 kbytes dsram, 2 kbytes psram asc0, asc1, ssc0, ssc1, can0, can1, iic
xc167-16 derivatives general device information data sheet 7 v1.2, 2006-03 2 general device information 2.1 introduction the xc167 derivatives are high-performance members of the infineon xc166 family of full featured single-chip cmos microcontrollers. these devi ces extend the functionality and performance of the c166 fami ly in terms of instructions (mac unit), peripherals, and speed. they combine hi gh cpu performance (up to 40 mill ion instructions per second) with high peripheral function ality and enhanced io-capabilitie s. they also provide clock generation via pll and vari ous on-chip memory module s such as program flash, program ram, and data ram. figure 1 logic symbol mca05554_7 xc167 xtal1 xtal2 xtal3 xtal4 nmi rstin rstout ea ready ale rd wr/wrl port 5 16 bit port 20 6 bit port0 16 bit port1 16 bit port 2 8 bit port 3 15 bit port 4 8 bit port 6 8 bit port 7 4 bit port 9 6 bit v agnd v aref v ddi/p v ssi/p jtag 5 bit trst debug 2 bit
xc167-16 derivatives general device information data sheet 8 v1.2, 2006-03 2.2 pin configuration and definition the pins of the xc167 are described in detail in table 2 , including all their alternate functions. figure 2 summarizes all pins in a condens ed way, showing their location on the 4 sides of the package. e* ) and c*) mark pins to be used as alternate external interrupt inputs, c*) marks pi ns that can have can interf ace lines assigned to them. figure 2 pin configuration (top view) mcp06458 tdo tms p3.12/bhe/wrh/e*) p3.13/sclk0/e*) p3.15/clkout/fout v ddi p5.5/an5 p5.4/an4 p5.3/an3 p5.2/an2 p5.1/an1 p5.0/an0 p9.5/scl2/cc21io p9.4/sda2/cc20io p9.3/scl1/cc19io/c*) p9.2/sda1/cc18io/c*) p9.1/scl0/cc17io/c*) p9.0/sda0/cc16io/c*) p7.7/cc31io/c*) p7.6/cc30io/c*) p7.5/cc29io/c*) p7.4/cc28io/c*) p6.7/breq/cc7io p6.6/hlda/cc6io p6.5/hold/cc5io p6.4/cs4/cc4io p6.3/cs3/cc3io p6.2/cs2/cc2io p6.1/cs1/cc1io p6.0/cs0/cc0io nmi p20.12/rstout n.c. n.c. v ddp v ssp v ddp v ssp v ddp v ssp p5.11/an11/t5eud p5.10/an10/t6eud p4.0/a16 v ssi p4.1/a17 p4.2/a18 p4.3/a19 p4.4/a20/c*) p4.5/a21/c*) p4.6/a22/c*) p4.7/a23/c*) v ddp v ssp p20.0/rd p20.1/wr/wrl p20.2/ready p20.4/ale p20.5/ea p0l.0/ad0 p0l.1/ad1 p0l.2/ad2 p0l.3/ad3 p0l.4/ad4 p0l.5/ad5 p0l.6/ad6 p0l.7/ad7 v ddp v ssp p0h.0/ad8 p0h.1/ad9 n.c. n.c. brkin brkout rstin xtal4 xtal3 v ssi xtal1 xtal2 v ssi v ddi p1h.7/a15/cc27io p1h.6/a14/cc26io p1h.5/a13/cc25io p1h.4/a12/cc24io p1h.3/a11/sclk1/e*) p1h.2/a10/cc6pos2/mtsr1 p1h.1/a9/cc6pos1/mrst1 p1h.0/a8/cc6pos0/cc23io/e*) v ssp v ddp p1l.7/a7/ctrap/cc22io p1l.6/a6/cout63 p1l.5/a5/cout62 p1l.4/a4/cc62 p1l.3/a3/cout61 p1l.2/a2/cc61 p1l.1/a1/cout60 p1l.0/a0/cc60 p0h.7/ad15 p0h.6/ad14 p0h.5/ad13 p0h.4/ad12 p0h.3/ad11 p0h.2/ad10 n.c. n.c. p2.15/cc15io/ex7in/t7in p5.8/an8 p5.9/an9 p5.6/an6 p5.7/an7 v aref v agnd p5.12/an12/t6in p5.13/an13/t5in p5.14/an14/t4eud p5.15/an15/t2eud v ssi v ddi p2.8/cc8io/ex0in p2.9/cc9io/ex1in p2.10/cc10io/ex2in p2.11/cc11io/ex3in p2.12/cc12io/ex4in p2.13/cc13io/ex5in p2.14/cc14io/ex6in trst v ddp p3.0/t0in/txd1/e*) p3.1/t6out/rxd1/e*) p3.2/capin p3.3/t3out p3.4/t3eud p3.5/t4in p3.6/t3in p3.7/t2in p3.8/mrst0 p3.9/mtsr0 p3.10/txd0/e*) p3.11/rxd0/e*) tck tdi xc167 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
xc167-16 derivatives general device information data sheet 9 v1.2, 2006-03 table 2 pin definitions and functions sym- bol pin num. input outp. function p20.12 3 io for details, please re fer to the de scription of p20 . nmi 4 i non-maskable interrupt input. a hi gh to low tran sition at this pin causes the cpu to vector to the nmi trap routine. when the pwrdn (power dow n) instruction is executed, the nmi pin must be low in order to force the xc167 into power down mode. if nmi is high, when pwrdn is executed, the part will continue to run in normal mode. if not used, pin nmi should be pulled high externally. p6 p6.0 p6.1 p6.2 p6.3 p6.4 p6.5 p6.6 p6.7 7 8 9 10 11 12 13 14 io o io o io o io o io o io i io i/o io o io port 6 is an 8-bit bi directional i/o por t. each pin can be programmed for inpu t (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). the input threshold of port 6 is selectable (standard or special). the port 6 pins also serv e for alternate functions: cs0 chip select 0 output, cc0io capcom1: cc0 capt ure inp./compare output cs1 chip select 1 output, cc1io capcom1: cc1 capt ure inp./compare output cs2 chip select 2 output, cc2io capcom1: cc2 capt ure inp./compare output cs3 chip select 3 output, cc3io capcom1: cc3 capt ure inp./compare output cs4 chip select 4 output, cc4io capcom1: cc4 capt ure inp./compare output hold external master ho ld request input, cc5io capcom1: cc5 capt ure inp./compare output hlda hold acknowledge outp ut (master mode) or input (slave mode), cc6io capcom1: cc6 capt ure inp./compare output breq bus request output, cc7io capcom1: cc7 capt ure inp./compare output
xc167-16 derivatives general device information data sheet 10 v1.2, 2006-03 p7 p7.4 p7.5 p7.6 p7.7 15 16 17 18 io i/o i i i/o o i i/o i i i/o o i port 7 is a 4-bit bidirectiona l i/o port. each pin can be programmed for inpu t (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). the input threshold of port 7 is selectable (standard or special). port 7 pins provide inputs/out puts for capcom2 and serial interface lines. 1) cc28io capcom2: cc28 capt ure inp./compare outp., can2_rxd can node 2 receive data input, ex7in fast external interrupt 7 input (alternate pin b) cc29io capcom2: cc29 capt ure inp./compare outp., can2_txd can node 2 transmit data output, ex6in fast external interrupt 6 input (alternate pin b) cc30io capcom2: cc30 capt ure inp./compare outp., can1_rxd can node 1 receive data input, ex7in fast external interrupt 7 input (alternate pin a) cc31io capcom2: cc31 capt ure inp./compare outp., can1_txd can node 1 transmit data output, ex6in fast external interrupt 6 input (alternate pin a) table 2 pin definitions and functions (cont?d) sym- bol pin num. input outp. function
xc167-16 derivatives general device information data sheet 11 v1.2, 2006-03 p9 p9.0 p9.1 p9.2 p9.3 p9.4 p9.5 21 22 23 24 25 26 io i/o i i/o i/o o i/o i/o i i/o i/o o i/o i/o i/o i/o i/o port 9 is a 6-bit bidirectiona l i/o port. each pin can be programmed for inpu t (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). the input threshold of port 9 is selectable (standard or special). the following po rt 9 pins also serve fo r alternate functions: 1) cc16io capcom2: cc16 capt ure inp./compare outp., can2_rxd can node 2 receive data input, sda0 iic bus data line 0 cc17io capcom2: cc17 capt ure inp./compare outp., can2_txd can node 2 transmit data output, scl0 iic bus clock line 0 cc18io capcom2: cc18 capt ure inp./compare outp., can1_rxd can node 1 receive data input, sda1 iic bus data line 1 cc19io capcom2: cc19 capt ure inp./compare outp., can1_txd can node 1 transmit data output, scl1 iic bus clock line 1 cc20io capcom2: cc20 capt ure inp./compare outp., sda2 iic bus data line 2 cc21io capcom2: cc21 capt ure inp./compare outp., scl2 iic bus clock line 2 table 2 pin definitions and functions (cont?d) sym- bol pin num. input outp. function
xc167-16 derivatives general device information data sheet 12 v1.2, 2006-03 p5 p5.0 p5.1 p5.2 p5.3 p5.4 p5.5 p5.10 p5.11 p5.8 p5.9 p5.6 p5.7 p5.12 p5.13 p5.14 p5.15 29 30 31 32 33 34 35 36 37 38 39 40 43 44 45 46 i i i i i i i i i i i i i i i i i port 5 is a 16-bit input-only port. the pins of port 5 also serve as analog input channels for the a/d converter, or they serve as timer inputs: an0 an1 an2 an3 an4 an5 an10, t6eud gpt1 timer t4 ext. up/down ctrl. inp. an11, t5eud gpt1 timer t2 ext. up/down ctrl. inp an8 an9 an6 an7 an12, t6in gpt2 timer t6 count/gate input an13, t5in gpt2 timer t5 count/gate input an14, t4eud gpt1 timer t4 ext. up/down ctrl. inp. an15, t2eud gpt1 timer t2 ext. up/down ctrl. inp. table 2 pin definitions and functions (cont?d) sym- bol pin num. input outp. function
xc167-16 derivatives general device information data sheet 13 v1.2, 2006-03 p2 p2.8 p2.9 p2.10 p2.11 p2.12 p2.13 p2.14 p2.15 49 50 51 52 53 54 55 56 io i/o i i/o i i/o i i/o i i/o i i/o i i/o i i/o i i port 2 is an 8-bit bi directional i/o por t. each pin can be programmed for inpu t (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). the input threshold of port 2 is selectable (standard or special). the following port 2 pins also serve for alternate functions: cc8io capcom1: cc8 captur e inp./compare output, ex0in fast external interru pt 0 input (default pin) cc9io capcom1: cc9 captur e inp./compare output, ex1in fast external interru pt 1 input (default pin) cc10io capcom1: cc10 capt ure inp./compare outp., ex2in fast external interru pt 2 input (default pin) cc11io capcom1: cc11 capt ure inp./compare outp., ex3in fast external interru pt 3 input (default pin) cc12io capcom1: cc12 capt ure inp./compare outp., ex4in fast external interru pt 4 input (default pin) cc13io capcom1: cc13 capt ure inp./compare outp., ex5in fast external interru pt 5 input (default pin) cc14io capcom1: cc14 capt ure inp./compare outp., ex6in fast external interru pt 6 input (default pin) cc15io capcom1: cc15 capt ure inp./compare outp., ex7in fast external interrupt 7 input (default pin), t7in capcom2: timer t7 count input trst 57 i test-system reset input. a hi gh-level at this pin activates the xc167?s debug system. note: for normal system operation, pin trst should be held low. table 2 pin definitions and functions (cont?d) sym- bol pin num. input outp. function
xc167-16 derivatives general device information data sheet 14 v1.2, 2006-03 p3 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p3.8 p3.9 p3.10 p3.11 p3.12 p3.13 p3.15 59 60 61 62 63 64 65 66 67 68 69 70 75 76 77 io i o i o i/o i i o i i i i i/o i/o o i i/o i o o i i/o i o o port 3 is a 15-bit bidirectional i/o port. each pin can be programmed for inpu t (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). the input threshold of port 3 is selectable (standard or special). the following port 3 pins also serve for alternate functions: t0in capcom1 timer t0 count input, txd1 asc1 clock/data output (async./sync), ex1in fast external interrupt 1 input (alternate pin b) t6out gpt2 timer t6 to ggle latch output, rxd1 asc1 data input (async. ) or inp./outp. (sync.), ex1in fast external interrupt 1 input (alternate pin a) capin gpt2 register c aprel capture input t3out gpt1 timer t3 toggle latch output t3eud gpt1 timer t3 exter nal up/down control input t4in gpt1 timer t4 coun t/gate/reload/capture inp t3in gpt1 timer t3 count/gate input t2in gpt1 timer t2 coun t/gate/reload/capture inp mrst0 ssc0 master-receive /slave-transmit in/out. mtsr0 ssc0 master-transmi t/slave-receive out/in. txd0 asc0 clock/data ou tput (async./sync.), ex2in fast external interrupt 2 input (alternate pin b) rxd0 asc0 data input (async. ) or inp./outp. (sync.), ex2in fast external interrupt 2 input (alternate pin a) bhe external memory high byte enable signal, wrh external memory high byte write strobe, ex3in fast external interrupt 3 input (alternate pin b) sclk0 ssc0 master clock ou tput/slave clock input., ex3in fast external interrupt 3 input (alternate pin a) clkout master clock output, fout programmable frequency output tck 71 i debug system: jtag clock input tdi 72 i debug system: jtag data in tdo 73 o debug system: jtag data out tms 74 i debug system: jtag test mode selection table 2 pin definitions and functions (cont?d) sym- bol pin num. input outp. function
xc167-16 derivatives general device information data sheet 15 v1.2, 2006-03 p4 p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 80 81 82 83 84 85 86 87 io o o o o o i i o i i o o i o i o i port 4 is an 8-bit bi directional i/o por t. each pin can be programmed for inpu t (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). the input threshold of port 4 is selectable (standard or special). port 4 can be used to output the segment addr ess lines, the optional chip select lines, and for serial interface lines: 1) a16 least significant segment address line a17 segment address line a18 segment address line a19 segment address line a20 segment address line, can2_rxd can node 2 receive data input, ex5in fast external interrupt 5 input (alternate pin b) a21 segment address line, can1_rxd can node 1 receive data input, ex4in fast external interrupt 4 input (alternate pin b) a22 segment address line, can1_txd can node 1 transmit data output, ex5in fast external interrupt 5 input (alternate pin a) a23 most significant segment address line, can1_rxd can node 1 receive data input, can2_txd can node 2 transmit data output, ex4in fast external interrupt 4 input (alternate pin a) table 2 pin definitions and functions (cont?d) sym- bol pin num. input outp. function
xc167-16 derivatives general device information data sheet 16 v1.2, 2006-03 p20 p20.0 p20.1 p20.2 p20.4 p20.5 p20.12 90 91 92 93 94 3 io o o i o i o port 20 is a 6-bit bidirectional i/o port. each pin can be programmed for inpu t (output driver in high-impedance state) or output. the input thre shold of port 20 is selectable (standard or special). the following port 20 pins also serve for alternate functions: rd external memory read strobe, activated for every external instructi on or data read access. wr /wrl external memory write strobe. in wr -mode this pin is activated for every external data write access. in wrl -mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. ready ready input. when the ready function is enabled, memory cycle time waitstates can be forced via this pin du ring an external access. ale address latch enable output. can be used for latchi ng the address into external memory or an address latch in the multiplexed bus modes. ea external access enable pin. a low-level at this pin during and after reset forces the xc167 to latc h the configuration from port0 and pin rd , and to begin instruction execution out of external memory. a high-level forces the xc167 to latch the configuration from pins rd , ale, and wr , and to begin instruction execut ion out of the internal program memory. ?romless? versions must have this pin tied to ?0?. rstout internal reset indication output. is activated asynchronously with an external hardware reset. it may also be activated (selectable) synchronous ly with an internal software or watchdog reset. is deactivated upon the execution of the einit instruction, optionally at the end of reset, or at any time (before einit) via user software. note: port 20 pins may input co nfiguration values (see ea ). table 2 pin definitions and functions (cont?d) sym- bol pin num. input outp. function
xc167-16 derivatives general device information data sheet 17 v1.2, 2006-03 port0 p0l.0 - p0l.7, p0h.0, p0h.1, p0h.2 - p0h.7 95 - 102, 105, 106, 111 - 116 io port0 consists of the two 8- bit bidirectional i/o ports p0l and p0h. each pin can be programmed for input (output driver in high-impedan ce state) or output. in case of an external bus co nfiguration, port0 serves as the address (a) and address/data (ad) bu s in multiplexed bus modes and as the data (d ) bus in demultiplexed bus modes. demultiplexed bus modes: 8-bit data bus: p0h = i/o, p0l = d7 - d0 16-bit data bus: p0h = d15 - d8, p0l = d7 - d0 multiplexed bus modes: 8-bit data bus: p0h = a1 5 - a8, p0l = ad7 - ad0 16-bit data bus: p0h = ad15 - ad8, p0l = ad7 - ad0 note: at the end of an external reset (ea = 0) port0 also may input configuration values. table 2 pin definitions and functions (cont?d) sym- bol pin num. input outp. function
xc167-16 derivatives general device information data sheet 18 v1.2, 2006-03 port1 p1l.0 p1l.1 p1l.2 p1l.3 p1l.4 p1l.5 p1l.6 p1l.7 p1h.0 p1h.1 p1h.2 p1h.3 p1h.4 p1h.5 p1h.6 p1h.7 117 118 119 120 121 122 123 124 127 128 129 130 131 132 133 134 io i/o o i/o o i/o o o i i/o i i i/o i i/o i i/o i/o i i/o i/o i/o i/o port1 consists of the two 8- bit bidirectional i/o ports p1l and p1h. each pin can be programmed for input (output driver in high-impedan ce state) or output. port1 is used as the 16-bit address bus (a) in demultiplexed bus modes (als o after switching from a demultiplexed to a multiplexed bus mode). the following port1 pins al so serve for alt. functions: cc60 capcom6: input / output of channel 0 cout60 capcom6: output of channel 0 cc61 capcom6: input / output of channel 1 cout61 capcom6: output of channel 1 cc62 capcom6: input / output of channel 2 cout62 capcom6: output of channel 2 cout63 output of 10-bit compare channel ctrap capcom2: cc22 captur e inp./compare outp. ctrap is an input pin with an internal pull-up resistor. a low level on this pin switches the capcom6 compare outputs to the logic level defined by softw are (if enabled). cc22io capcom2: cc22 capt ure inp./compare outp. cc6pos0 capcom6: position 0 input, ex0in fast external interrupt 0 input (alternate pin b), cc23io capcom2: cc23 capt ure inp./compare outp. cc6pos1 capcom6: position 1 input, mrst1 ssc1 master-receive /slave-transmit in/out. cc6pos2 capcom6: position 2 input, mtsr1 ssc1 master-transmi t/slave-receive out/inp. sclk1 ssc1 master clock ou tput / slave clock input, ex0in fast external interrupt 0 input (alternate pin a) cc24io capcom2: cc24 capt ure inp./compare outp. cc25io capcom2: cc25 capt ure inp./compare outp. cc26io capcom2: cc26 capt ure inp./compare outp. cc27io capcom2: cc27 capt ure inp./compare outp. table 2 pin definitions and functions (cont?d) sym- bol pin num. input outp. function
xc167-16 derivatives general device information data sheet 19 v1.2, 2006-03 xtal2 xtal1 137 138 o i xtal2: output of the main o scillator amplifier circuit xtal1: input to the ma in oscillator amp lifier and input to the internal clock generator to clock the device from an external source, drive xtal1, while leaving xtal2 unconnec ted. minimum and maximum high/low and rise/fall times specified in the ac characteristics must be observed. xtal3 xtal4 140 141 i o xtal3: input to the au xiliary (32-khz) o scillator amplifier xtal4: output of the auxili ary (32-khz) oscillator amplifier circuit to clock the device from an external source, drive xtal3, while leaving xtal4 unconnec ted. minimum and maximum high/low and rise/fall times specified in the ac characteristics must be observed. rstin 142 i reset input with schmitt-trig ger characteristics. a low-level at this pin while the oscillator is running resets the xc167. a spike filter suppre sses input pulses < 10 ns. input pulses > 100 ns safely pass the filter . the minimum duration for a safe recognition should be 100 ns + 2 cpu clock cycles. note: the reset duration must be sufficient to let the hardware configurat ion signals settle. external circuitry must g uarantee low-level at the rstin pin at least until both power supply voltages have reached the operating range. brk out 143 o debug system: break out brkin 144 i debug system: break in nc 1, 2, 107 - 110 ? no connection. it is recommended not to con nect these pins to the pcb. v aref 41 ? reference voltage for the a/d converter. v agnd 42 ? reference ground for the a/d converter. v ddi 48, 78, 135 ? digital core supply voltage (on-chip modules): +2.5 v during normal o peration and idle mode. please refer to the operating conditions . table 2 pin definitions and functions (cont?d) sym- bol pin num. input outp. function
xc167-16 derivatives general device information data sheet 20 v1.2, 2006-03 v ddp 6, 20, 28, 58, 88, 103, 125 ? digital pad supply voltag e (pin output drivers): +5 v during normal oper ation and idle mode. please refer to the operating conditions . v ssi 47, 79, 136, 139 ? digital ground connect decoupling ca pacitors to adjacent v dd / v ss pin pairs as close as possible to the pins. all v ss pins must be connected to the ground-line or ground- plane. v ssp 5, 19, 27, 89, 104, 126 ? 1) the can interface lines are assigned to po rts p4, p7, and p9 under software control. table 2 pin definitions and functions (cont?d) sym- bol pin num. input outp. function
xc167-16 derivatives functional description data sheet 21 v1.2, 2006-03 3 functional description the architecture of the xc167 combines advantages of risc, cisc, and dsp processors with an advanced peripheral subsystem in a very well-balanced way. in addition, the on-chip memory blocks allow the design of compact systems-on-silicon with maximum performance (computi ng, control, communication). the on-chip memory blocks (program code-memory and sram, dual-port ram, data sram) and the set of generic peripherals ar e connected to the cp u via separate buses. another bus, the lxbus, conn ects additional on-chip reso urces as well as external resources (see figure 3 ). this bus structure enhances the overall system performanc e by enabling the concurrent operation of several su bsystems of the xc167. the following block diagram gi ves an overview of the diff erent on-chip components and of the advanced, high b andwidth internal bus st ructure of the xc167. figure 3 block diagram interrupt bus xtal mcb04323_x7.vsd osc / pll clock generation rtc wdt gpt t2 t3 t4 t5 t6 ssc0 brgen (spi) asc1 brgen (usart) adc 8/10-bit 16 channels cc2 t7 t8 ebc xbus control external bus control progmem flash 128 kbytes p 20 4 16 port 5 16 psram dpram dsram c166sv2-core pmu dmu cpu asc0 brgen (usart) iic brgen ssc1 brgen (spi) cc1 t0 t1 twin can a b port1 port0 port 2 port 3 port 4 port 6 p 7 port 9 16 8 15 8 8 6 6 interrupt & pec peripheral data bus ocds debug support cc6 t12 t13
xc167-16 derivatives functional description data sheet 22 v1.2, 2006-03 3.1 memory subsystem and organization the memory space of the xc167 is configur ed in a von neumann architecture, which means that all internal and external resources, such as code memory, data memory, registers and i/o ports, are organized with in the same linear address space. this common memory space includes 16 mbytes and is arranged as 256 segments of 64 kbytes each, where each segment consists of four data pages of 16 kbytes each. the entire memory space ca n be accessed bytewise or wordwise. portions of the on-chip dpram and the register spaces (e/s fr) have additionally been made directly bitaddressable. the internal data memory areas and the sp ecial function register areas (sfr and esfr) are mapped into segm ent 0, the system segment. the program management unit (pmu) handles all code fetches and, therefore, controls accesses to the program memories, such as flash memory and psram. the data management unit (d mu) handles all data transf ers and, therefore, controls accesses to the dsram and the on-chip peripherals. both units (pmu and dmu) are connected via the high-spe ed system bus to exchange data. this is required if operands are read fr om program memory, code or data is written to the psram, code is fetched from external memory, or data is read from or written to external resources, including peripherals on the lxbus (s uch as twincan). the system bus allows concurrent two-way communica tion for maximum tr ansfer performance. 128 kbytes of on-chip flash memory store code or constant data. the on-chip flash memory is organized as four 8-kbyte sect ors, one 32-kbyte se ctor, and one 64-kbyte sector. each sector can be separately write protected 1) , erased and programmed (in blocks of 128 bytes). the co mplete flash area can be read-protected. a password sequence temporarily unlocks pr otected areas. the flash m odule combines very fast 64-bit one-cycle read access es with protected and effi cient writing algorithms for programming and erasing. thus , program execution out of th e internal flash results in maximum performance. dyna mic error correction provid es extremely high read data security for a ll read accesses. for timing characterist ics, please refer to section 4.4.2 . 2 kbytes of on-chip program sram (psram) are provided to store user code or data. the psram is accessed via the pmu and is therefore optimized for code fetches. 4 kbytes of on-chip data sram (dsram) are provided as a st orage for general user data. the dsram is accessed via the dm u and is therefore optimized for data accesses. 2 kbytes of on-chip dual-port ram (dpram) are provided as a storage for user defined variables, for the syst em stack, and general purpos e register banks. a register bank can consist of up to 16 wordwide (r0 to r15) and/or bytewide (rl0, rh0, ?, rl7, 1) each two 8-kbyte sectors are comb ined for write-protection purposes.
xc167-16 derivatives functional description data sheet 23 v1.2, 2006-03 rh7) so-called general purpose registers (gprs). the upper 256 bytes of the dpram are direct ly bitaddressable. wh en used by a gpr, any location in the dp ram is bitaddressable. 1024 bytes (2 512 bytes) of the address space are rese rved for the special function register areas (sfr space and esfr space) . sfrs are wordwide registers which are used for controlling and monitori ng functions of the differen t on-chip units. unused sfr addresses are reserved for fu ture members of the xc166 family. therefore, they should either not be accessed, or written with zeros, to en sure upward compatibility. in order to meet the needs of designs wher e more memory is required than is provided on chip, up to 12 mbytes (approximately, see table 3 ) of external ram and/or rom can be connected to the microcontrol ler. the external bus interf ace also provides access to external peripherals. table 3 xc167 memory map 1) 1) accesses to the shaded areas generate external bus accesses. address area start loc. end loc. area size 2) 2) the areas marked with ? xc167-16 derivatives functional description data sheet 24 v1.2, 2006-03 3.2 external bus controller all of the external memory accesses are perf ormed by a particular on-chip external bus controller (ebc). it can be programmed either to single chip mode when no external memory is required, or to one of four different external memory access modes 1) , which are as follows: ? 16 ? 24-bit addresses, 16-bit data, demultiplexed ? 16 ? 24-bit addresses, 16-bit data, multiplexed ? 16 ? 24-bit addresses, 8-bit data, multiplexed ? 16 ? 24-bit addresses, 8-bit data, demultiplexed in the demultiplexed bus modes, address es are output on port1 and data is input/output on port0 or p0l, respecti vely. in the multip lexed bus modes both addresses and data use port0 for input/out put. the high order address (segment) lines use port 4. the number of active segment ad dress lines is select able, restricting the external address space to 8 mbytes ? 64 kbytes . this is required when interface lines are assigned to port 4. up to 5 external cs signals (4 windows plus default) can be generated in order to save external glue logic. external modules can directly be conne cted to the common address/data bus and their individua l select lines. access to very slow memories or modules with varying a ccess times is supported via a particular ?ready? function. the active leve l of the control input signal is selectable. a hold /hlda protocol is available fo r bus arbitration and allows the sharing of external resources with other bus mast ers. the bus arbitration is enabled by software. after enabling, pins p6.7 ? p6.5 (breq , hlda , hold ) are automatically controlled by the ebc. in master mode (defau lt after reset) the hlda pin is an output. in slave mode pin hlda is switched to input. this allows the direct connection of the slave controller to another master controll er without glue logic. important timing characteristics of the external bus interface have been made programmable (via registers tconcsx/fconcsx) to allow the user the adaption of a wide range of different types of memories and external peripherals. in addition, up to 4 indepe ndent address windows may be defined (via registers addrselx) which control the access to different reso urces with different bus characteristics. these addre ss windows are arranged hierarchically where window 4 overrides window 3, and wi ndow 2 overrides window 1. al l accesses to locations not covered by these 4 address windows are controlled by tconcs0/fconcs0. the currently active window can ge nerate a chip select signal. the external bus timing is related to the risi ng edge of the re ference clock output clkout. the external bus protocol is compatib le with that of the standard c166 family. 1) bus modes are switched dynamically if several address windows with different mode settings are used.
xc167-16 derivatives functional description data sheet 25 v1.2, 2006-03 the ebc also controls accesses to resour ces connected to the on-chip lxbus. the lxbus is an internal re presentation of the external bu s and allows ac cessing integrated peripherals and modules in the sa me way as extern al components. the twincan module is connec ted and accessed via the lxbus.
xc167-16 derivatives functional description data sheet 26 v1.2, 2006-03 3.3 central processing unit (cpu) the main core of the cpu co nsists of a 5-stage executio n pipeline with a 2-stage instruction-fetch pipeline, a 16- bit arithmetic and logic unit (alu), a 32-bit/40-bit multiply and accumulate unit (mac), a re gister-file providing three re gister banks, and dedicated sfrs. the alu features a multiply and divi de unit, a bit-mask ge nerator, and a barrel shifter. figure 4 cpu block diagram based on these hardware provisions, most of the xc167?s instructions can be executed in just one machine cycle which requires 25 ns at 40 mhz cpu clock. for example, shift dpram cpu ipip rf r0 r1 gprs r14 r15 r0 r1 gprs r14 r15 ifu injection/ exception handler adu mac mca04917_x.vsd cpucon1 cpucon2 csp ip return stack fifo branch unit prefetch unit vecseg tfr +/- idx0 idx1 qx0 qx1 qr0 qr1 dpp0 dpp1 dpp2 dpp3 spseg sp stkov stkun +/- mrw mcw msw mal +/- mah m ultiply unit alu division unit m ultiply u nit bit-mask-gen. barrel-shifter +/- mdc psw mdh zeros mdl ones r0 r1 gprs r14 r15 cp wb buffer 2-stage prefetch pipeline 5-stage pipeline r0 r1 gprs r14 r15 pmu dmu dsram ebc peripherals psram flash/rom
xc167-16 derivatives functional description data sheet 27 v1.2, 2006-03 and rotate instructions ar e always processed during one machine cycle independent of the number of bits to be shi fted. also multiplication and most mac instructions execute in one single cycle. a ll multiple-cycle instruct ions have been optimize d so that they can be executed very fast as well: for example, a division algorithm is performed in 18 to 21 cpu cycles, depending on the data and division type. four cycles are always visible, the rest runs in the background. another pipeline optimization, the branch target prediction, allows eliminating the execution time of bran ch instructions if the prediction was correct. the cpu has a register context consisting of up to three register banks with 16 wordwide gprs each at its disposal. the global register bank is physi cally allocated within the on- chip dpram area. a context pointer (cp) r egister determines the base address of the active global register bank to be accessed by the cp u at any time. the number of register banks is only restricted by the available intern al ram space. for easy parameter passing, a register bank may overlap others. a system stack of up to 32 kwords is prov ided as a storage fo r temporary data. the system stack can be allo cated to any loca tion within the address space (preferably in the on-chip ram area), and it is accessed by th e cpu via the stack po inter (sp) register. two separate sfrs, stkov and stkun, ar e implicitly compared against the stack pointer value upon each stack access for the detection of a st ack overflow or underflow. the high performance offered by the hardware implementation of th e cpu can efficiently be utilized by a programmer via the highly efficient xc167 instruct ion set which includes the following instruction classes: ? standard arithmetic instructions ? dsp-oriented arithmetic instructions ? logical instructions ? boolean bit manipula tion instructions ? compare and loop co ntrol instructions ? shift and rotate instructions ? prioritize instruction ? data movement instructions ? system stack instructions ? jump and call instructions ? return instructions ? system control instructions ? miscellaneous instructions the basic instruction length is either 2 or 4 bytes. possibl e operand types are bits, bytes and words. a variety of direc t, indirect or immediate addressing modes are provided to specify the required operands.
xc167-16 derivatives functional description data sheet 28 v1.2, 2006-03 3.4 interrupt system with an interrupt response time of typically 8 cpu clocks (in case of internal program execution), the xc167 is capable of reacti ng very fast to the occurrence of non- deterministic events. the architecture of the xc 167 supports several mechanis ms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontrol ler. any of these interrupt requests can be programmed to being serviced by the interrupt controller or by the peripheral event controller (pec). in contrast to a standard interrupt service where the current program execution is suspended and a branch to th e interrupt vector table is performed, just one cycle is ?stolen? from the current cpu activity to perform a pec serv ice. a pec service implies a single byte or word data tran sfer between any two memory locations with an additional increment of either the pec so urce, or the destination pointer , or both. an individual pec transfer counter is implicitly decremented for each pec service except when performing in the continuous transfer m ode. when this counter reache s zero, a standard interrupt is performed to the corresponding source related vector loca tion. pec services are very well suited, for example, for supporting the transmission or reception of blocks of data. the xc167 has 8 pec channels each of whic h offers such fast interrupt-driven data transfer capabilities. a separate control register wh ich contains an interrupt requ est flag, an interrupt enable flag and an interrupt priority bi tfield exists for each of the po ssible interrupt nodes. via its related register, each node ca n be programmed to one of sixt een interrupt priority levels. once having been accepted by the cpu, an interrupt servic e can only be interrupted by a higher prioritized service request. for th e standard interrupt pr ocessing, each of the possible interrupt nodes has a dedicated vector location. fast external interrupt inputs are provided to service external interrupts with high precision requirements. these fast in terrupt inputs featur e programmable edge detection (rising edge, fall ing edge, or both edges). software interrupts are supported by means of the ?trap? instruction in combination with an individual trap (interrupt) number. table 4 shows all of the possibl e xc167 interrupt source s and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers. note: interrupt nodes which are not assig ned to peripherals (u nassigned nodes), may be used to generate softwa re controlled interrupt requests by setting the respective interrupt request bit (xir).
xc167-16 derivatives functional description data sheet 29 v1.2, 2006-03 table 4 xc167 interrupt nodes source of interrupt or pec service request control register vector location 1) trap number capcom register 0 cc1_cc0ic xx?0040 h 10 h / 16 d capcom register 1 cc1_cc1ic xx?0044 h 11 h / 17 d capcom register 2 cc1_cc2ic xx?0048 h 12 h / 18 d capcom register 3 cc1_cc3ic xx?004c h 13 h / 19 d capcom register 4 cc1_cc4ic xx?0050 h 14 h / 20 d capcom register 5 cc1_cc5ic xx?0054 h 15 h / 21 d capcom register 6 cc1_cc6ic xx?0058 h 16 h / 22 d capcom register 7 cc1_cc7ic xx?005c h 17 h / 23 d capcom register 8 cc1_cc8ic xx?0060 h 18 h / 24 d capcom register 9 cc1_cc9ic xx?0064 h 19 h / 25 d capcom register 10 cc1_cc10ic xx?0068 h 1a h / 26 d capcom register 11 cc1_cc11ic xx?006c h 1b h / 27 d capcom register 12 cc1_cc12ic xx?0070 h 1c h / 28 d capcom register 13 cc1_cc13ic xx?0074 h 1d h / 29 d capcom register 14 cc1_cc14ic xx?0078 h 1e h / 30 d capcom register 15 cc1_cc15ic xx?007c h 1f h / 31 d capcom register 16 cc2_cc16ic xx?00c0 h 30 h / 48 d capcom register 17 cc2_cc17ic xx?00c4 h 31 h / 49 d capcom register 18 cc2_cc18ic xx?00c8 h 32 h / 50 d capcom register 19 cc2_cc19ic xx?00cc h 33 h / 51 d capcom register 20 cc2_cc20ic xx?00d0 h 34 h / 52 d capcom register 21 cc2_cc21ic xx?00d4 h 35 h / 53 d capcom register 22 cc2_cc22ic xx?00d8 h 36 h / 54 d capcom register 23 cc2_cc23ic xx?00dc h 37 h / 55 d capcom register 24 cc2_cc24ic xx?00e0 h 38 h / 56 d capcom register 25 cc2_cc25ic xx?00e4 h 39 h / 57 d capcom register 26 cc2_cc26ic xx?00e8 h 3a h / 58 d capcom register 27 cc2_cc27ic xx?00ec h 3b h / 59 d capcom register 28 cc2_cc28ic xx?00f0 h 3c h / 60 d
xc167-16 derivatives functional description data sheet 30 v1.2, 2006-03 capcom register 29 cc2_cc29ic xx?0110 h 44 h / 68 d capcom register 30 cc2_cc30ic xx?0114 h 45 h / 69 d capcom register 31 cc2_cc31ic xx?0118 h 46 h / 70 d capcom timer 0 cc1_t0ic xx?0080 h 20 h / 32 d capcom timer 1 cc1_t1ic xx?0084 h 21 h / 33 d capcom timer 7 cc2_t7ic xx?00f4 h 3d h / 61 d capcom timer 8 cc2_t8ic xx?00f8 h 3e h / 62 d gpt1 timer 2 gpt12e_t2ic xx?0088 h 22 h / 34 d gpt1 timer 3 gpt12e_t3ic xx?008c h 23 h / 35 d gpt1 timer 4 gpt12e_t4ic xx?0090 h 24 h / 36 d gpt2 timer 5 gpt12e_t5ic xx?0094 h 25 h / 37 d gpt2 timer 6 gpt12e_t6ic xx?0098 h 26 h / 38 d gpt2 caprel register gpt12e_cric xx?009c h 27 h / 39 d a/d conversion comp lete adc_cic xx?00a0 h 28 h / 40 d a/d overrun error adc_eic xx?00a4 h 29 h / 41 d asc0 transmit asc0_tic xx?00a8 h 2a h / 42 d asc0 transmit buffer asc0_tbic xx?011c h 47 h / 71 d asc0 receive asc0_ric xx?00ac h 2b h / 43 d asc0 error asc0_eic xx?00b0 h 2c h / 44 d asc0 autobaud asc0_abic xx?017c h 5f h / 95 d ssc0 transmit ssc0_tic xx?00b4 h 2d h / 45 d ssc0 receive ssc0_ric xx?00b8 h 2e h / 46 d ssc0 error ssc0_eic xx?00bc h 2f h / 47 d iic data transfer event iic_dtic xx?0100 h 40 h / 64 d iic protocol event iic_peic xx?0104 h 41 h / 65 d pll/owd pllic xx?010c h 43 h / 67 d asc1 transmit asc1_tic xx?0120 h 48 h / 72 d asc1 transmit buffer asc1_tbic xx?0178 h 5e h / 94 d asc1 receive asc1_ric xx?0124 h 49 h / 73 d asc1 error asc1_eic xx?0128 h 4a h / 74 d table 4 xc167 interrupt nodes (cont?d) source of interrupt or pec service request control register vector location 1) trap number
xc167-16 derivatives functional description data sheet 31 v1.2, 2006-03 asc1 autobaud asc1_abic xx?0108 h 42 h / 66 d end of pec subc hannel eopic xx?0130 h 4c h / 76 d capcom6 timer t1 2 ccu6_t12ic xx?0134 h 4d h / 77 d capcom6 timer t1 3 ccu6_t13ic xx?0138 h 4e h / 78 d capcom6 emergency ccu6_eic xx?013c h 4f h / 79 d capcom6 ccu6_ic xx?0140 h 50 h / 80 d ssc1 transmit ssc1_tic xx?0144 h 51 h / 81 d ssc1 receive ssc1_ric xx?0148 h 52 h / 82 d ssc1 error ssc1_eic xx?014c h 53 h / 83 d can0 can_0ic xx?0150 h 54 h / 84 d can1 can_1ic xx?0154 h 55 h / 85 d can2 can_2ic xx?0158 h 56 h / 86 d can3 can_3ic xx?015c h 57 h / 87 d can4 can_4ic xx?0164 h 59 h / 89 d can5 can_5ic xx?0168 h 5a h / 90 d can6 can_6ic xx?016c h 5b h / 91 d can7 can_7ic xx?0170 h 5c h / 92 d rtc rtc_ic xx?0174 h 5d h / 93 d unassigned node ? xx?012c h 4b h / 75 d unassigned node ? xx?00fc h 3f h / 63 d unassigned node ? xx?0160 h 58 h / 88 d 1) register vecseg defines the segment where the vector table is located to. bitfield vecsc in register cpuc on1 defines the distance between two adjacent vectors. this table represents the default setting, with a dist ance of 4 (two words) between two vectors. table 4 xc167 interrupt nodes (cont?d) source of interrupt or pec service request control register vector location 1) trap number
xc167-16 derivatives functional description data sheet 32 v1.2, 2006-03 the xc167 also provides an excellent mechanism to identi fy and to process exceptions or error conditions that ar ise during run-time, so-calle d ?hardware traps?. hardware traps cause immediate non-maskable system reaction which is si milar to a standard interrupt service (branching to a dedicated vector table location). the occurrence of a hardware trap is additionally sign ified by an individual bit in the trap flag register (tfr). except when another higher pr ioritized trap service is in pr ogress, a hardware trap will interrupt any actual program execution. in turn, hardware trap services can normally not be interrupted by standard or pec interrupts. table 5 shows all of the possible e xceptions or error conditions that can arise during run- time: table 5 hardware trap summary exception condition trap flag trap vector vector location 1) 1) register vecseg defines the segment where the vector table is located to. trap number trap priority reset functions: ? hardware reset ? software reset ? watchdog timer overflow ? reset reset reset xx?0000 h xx?0000 h xx?0000 h 00 h 00 h 00 h iii iii iii class a hardware traps: ? non-maskable interrupt ? stack overflow ? stack underflow ? software break nmi stkof stkuf softbrk nmitrap stotrap stutrap sbrktrap xx?0008 h xx?0010 h xx?0018 h xx?0020 h 02 h 04 h 06 h 08 h ii ii ii ii class b hardware traps: ? undefined opcode ? pmi access error ? protected instruction fault ? illegal word operand access undopc pacer prtflt illopa btrap btrap btrap btrap xx?0028 h xx?0028 h xx?0028 h xx?0028 h 0a h 0a h 0a h 0a h i i i i reserved ? ? [2c h - 3c h ][0b h - 0f h ] ? software traps ? trap instruction ?? any [xx?0000 h - xx?01fc h ] in steps of 4 h any [00 h - 7f h ] current cpu priority
xc167-16 derivatives functional description data sheet 33 v1.2, 2006-03 3.5 on-chip debug support (ocds) the on-chip debug support system provides a broad range of debug and emulation features built into the xc167. the user so ftware running on th e xc167 can thus be debugged within the target system environment. the ocds is controlled by an external debugging device via the debug interface, consisting of the ieee-1149-c onforming jtag port and a br eak interface. the debugger controls the ocds via a set of dedicated re gisters accessible via the jtag interface. additionally, the ocds system can be controlled by the cpu, e.g. by a monitor program. an injection interface allows the execution of ocds-generated instructions by the cpu. multiple breakpoints can be triggered by on-chip hardware, by software, or by an external trigger input. single stepping is sup ported as well as the injection of arbitrary instructions and read/write a ccess to the complete internal address space. a breakpoint trigger can be answered with a cpu-halt, a monitor call, a data transfer, or/and the activation of an external signal. tracing data can be obtained via the jtag in terface or via the exte rnal bus interface for increased performance. the debug interface uses a set of 6 interface sign als (4 jtag lines, 2 break lines) to communicate with external circuitry. these interface signals use dedicated pins. complete system emulation is supported by the new em ulation technology (net) interface.
xc167-16 derivatives functional description data sheet 34 v1.2, 2006-03 3.6 capture/compare units (capcom1/2) the capcom units support generation and control of timing sequences on up to 32 channels with a maximum re solution of 1 system clock cy cle (8 cycles in staggered mode). the capcom units are typically us ed to handle high sp eed i/o tasks such as pulse and waveform generation, pulse width modulation (pmw ), digital to analog (d/a) conversion, software timing , or time recording relati ve to external events. four 16-bit timers (t0/t1, t7/t8) with reload registers prov ide two independent time bases for each capture/ compare register array. the input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an over flow/underflow of timer t6 in module gpt2. this provides a wide range of variation for th e timer period and re solution and allows precise adjustments to the appl ication specific requirements . in addition, external count inputs for capcom timers t0 and t7 allow event schedu ling for the capture/compare registers relative to external events. both of the two capture/compare regist er arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either capcom timer t0 or t1 (t7 or t8, resp ectively), and programmed for capture or compare function. all registers of each module have each one port pin associat ed with it which serves as an input pin for triggering the capture functi on, or as an output pin to indicate the occurrence of a compare event. table 6 compare modes (capcom1/2) compare modes function mode 0 interrupt- only compare mode; several compare interrupts pe r timer period are possible mode 1 pin toggles on each compare match; several compare events per timer period are possible mode 2 interrupt- only compare mode; only one compare interrupt per timer period is generated mode 3 pin set ?1? on ma tch; pin reset ?0? on compare timer overflow; only one compare event per ti mer period is generated double register mode two registers operate on one pin; pin toggles on ea ch compare match; several compare events per timer period are possible single event mode generates single edges or pulses; can be used with any compare mode
xc167-16 derivatives functional description data sheet 35 v1.2, 2006-03 when a capture/compare register has been selected for capture mode, the current contents of the allo cated timer will be latc hed (?captured?) into the capture/compare register in response to an ex ternal event at the port pin which is associated with this register. in addition, a specif ic interrupt request for this capture/compare register is generated. either a po sitive, a negative, or both a positi ve and a negative external signal transition at the pin can be se lected as the triggering event. the contents of all registers which have been selected for on e of the five compare modes are continuously compared with the contents of the allocated timers. when a match occurs between the timer value and the va lue in a capture/compare register, specific actions will be taken based on th e selected compare mode.
xc167-16 derivatives functional description data sheet 36 v1.2, 2006-03 figure 5 capcom1/2 unit block diagram sixteen 16-bit capture/ compare registers mode control (capture or compare) t0/t7 input control t1/t8 input control mcb05569 ccxirq ccxirq ccxirq capcom1 provides channels x = 0 ? 15, capcom2 provides channels x = 16 ? 31. (see signals ccxio and ccxirq) t0irq, t7irq t1irq, t8irq ccxio ccxio ccxio t0in/t7in t6ouf f cc t6ouf f cc reload reg. t0rel/t7rel timer t0/t7 timer t1/t8 reload reg. t1rel/t8rel
xc167-16 derivatives functional description data sheet 37 v1.2, 2006-03 3.7 the capture/compare unit capcom6 the capcom6 unit supports generation and co ntrol of timing sequences on up to three 16-bit capture/compare ch annels plus one independent 10-bit comp are channel. in compare mode the capcom6 unit provid es two output signal s per channel which have inverted polarity and no n-overlapping pulse transitions (deadtime control). the compare channel can generate a single pwm output sig nal and is further used to modulate the capture/co mpare output signals. in capture mode the contents of compare timer t12 is stored in the capture registers upon a signal tran sition at pins ccx. compare timers t12 (16-bit) and t13 (10-bit) are free running timers which are clocked by the prescaled system clock. figure 6 capcom6 block diagram for motor control applications both subunits ma y generate versatile multichannel pwm signals which are basically eith er controlled by compare ti mer t12 or by a typical hall sensor pattern at the interrupt inputs (block commutation). control cc channel 0 cc60 cc channel 1 cc61 cc channel 2 cc62 mcb04109 prescaler offset register t12of compare timer t12 16-bit period register t12p mode select register cc6msel trap register port control logic control register ctcon compare register cmp13 prescaler compare timer t13 10-bit period register t13p block commutation control cc6mcon.h cc60 cout60 cc61 cout61 cc62 cout62 ctrap cc6pos0 cc6pos1 cc6pos2 f cpu f cpu the timer registers (t12, t13) are not directly accessible. the period and offset registers are loading a value into the timer registers. cout63
xc167-16 derivatives functional description data sheet 38 v1.2, 2006-03 3.8 general purpose timer (gpt12e) unit the gpt12e unit represents a very flexible multifunctional timer/c ounter structure which may be used for many different time rela ted tasks such as event timing and counting, pulse width and duty cycle me asurements, pulse generation , or pulse multiplication. the gpt12e unit incorporates five 16-bit timers which are organ ized in two separate modules, gpt1 and gpt2. each timer in each module may operate independently in a number of different modes, or may be co ncatenated with another timer of the same module. each of the three ti mers t2, t3, t4 of module gpt1 can be configured individually for one of four basic modes of operation, which are timer, gated timer, counter, and incremental interface mode. in timer mode, the in put clock for a timer is derived from the system clock, divided by a programmable prescaler, while counter mode allows a timer to be clocked in refe rence to external events. pulse width or duty cycle meas urement is supported in ga ted timer mode, where the operation of a timer is controlled by the ?gat e? level on an external input pin. for these purposes, each timer has one a ssociated port pin (txin) which serves as gate or clock input. the maximum reso lution of the timers in module gpt1 is 4 system clock cycles. the count direction (up/down ) for each timer is progra mmable by software or may additionally be altered dyna mically by an external sign al on a port pin (txeud) to facilitate e.g. position tracking. in incremental interface mode the gpt1 timers (t2, t3, t4) can be directly connected to the incremental posi tion sensor signals a and b via their respecti ve inputs txin and txeud. direction and count signals are intern ally derived from these two input signals, so the contents of the respec tive timer tx corresponds to the sensor position. the third position sensor signal top0 can be connected to an interrupt input. timer t3 has an output toggle latch (t3otl) which changes its state on each timer overflow/underflow. the state of this latch may be output on pin t3out e.g. for time out monitoring of external hardware components. it may also be used internally to clock timers t2 and t4 for m easuring long time periods with high resolution. in addition to their basic op erating modes, timers t2 and t4 may be configured as reload or capture registers for timer t3. when used as capture or reload registers, timers t2 and t4 are stopped. the c ontents of timer t3 is captured into t2 or t4 in response to a signal at their associated input pins (txin). timer t3 is re loaded with the contents of t2 or t4 triggered either by an ex ternal signal or by a selectable state transition of its toggle latch t3otl. when both t2 and t4 are config ured to alternately reload t3 on opposite state transitions of t3otl with the low and high times of a pwm signal, this signal can be constantly generated with out software intervention.
xc167-16 derivatives functional description data sheet 39 v1.2, 2006-03 figure 7 block diagram of gpt1 with its maximum resolution of 2 system clock cycles, the gpt2 module provides precise event control and time measurement. it includes two ti mers (t5, t6) and a capture/reload register (caprel). both timers can be cl ocked with an input clock which is derived from the cpu clock via a programmable prescaler or with external signals. the mca05563 aux. timer t2 2 n :1 t2 mode control capture u/d basic clock f gpt t3con.bps1 t3otl t3out toggle latch t2in t2eud reload core timer t3 t3 mode control t3in t3eud u/d interrupt request (t3irq) t4 mode control u/d aux. timer t4 t4eud t4in reload capture interrupt request (t4irq) interrupt request (t2irq)
xc167-16 derivatives functional description data sheet 40 v1.2, 2006-03 count direction (up/down) fo r each timer is programma ble by software or may additionally be altered dynamically by an external signal on a port pin (txeud). concatenation of the timers is supported via the output togg le latch (t6otl) of timer t6, which changes its state on ea ch timer overflow/underflow. the state of this latch may be used to clock timer t5, and/ or it may be output on pin t6out. the overflows/underflo ws of timer t6 can additi onally be used to clock the capcom1/2 timers, and to cause a re load from the ca prel register. the caprel register may capt ure the contents of timer t5 based on an external signal transition on the corresponding port pin (c apin), and timer t5 may optionally be cleared after the capture procedure. this allows th e xc167 to measure absolute time differences or to perform pulse multiplica tion without software overhead. the capture trigger (timer t5 to caprel) may also be ge nerated upon transitions of gpt1 timer t3?s inputs t3in and/or t3e ud. this is especially advantageous when t3 operates in incremental interface mode.
xc167-16 derivatives functional description data sheet 41 v1.2, 2006-03 figure 8 block diagram of gpt2 mca05564 gpt2 timer t5 2 n :1 t5 mode control gpt2 caprel t3in/ t3eud caprel mode control t6 mode control reload clear u/d capture clear u/d t5in capin interrupt request (t5ir) interrupt request (t6ir) interrupt request (crir) basic clock f gpt t6con.bps2 t6in gpt2 timer t6 t6otl t6out t6ouf toggle ff
xc167-16 derivatives functional description data sheet 42 v1.2, 2006-03 3.9 real time clock the real time clock (rtc) modu le of the xc167 is directly clocked via a separate clock driver either with the on-chip auxiliary oscill ator frequency ( f rtc = f osca ) or with the prescaled on-chip main oscillator frequency ( f rtc = f oscm /32). it is ther efore independent from the selected clock gener ation mode of the xc167. the rtc basically consists of a chain of divider blocks: ? a selectable 8:1 divider (on - off) ? the reloadable 16-bit timer t14 ? the 32-bit rtc timer block (accessible via registers rtch and rtcl), made of: ? a reloadable 10-bit timer ? a reloadable 6-bit timer ? a reloadable 6-bit timer ? a reloadable 10-bit timer all timers count up. each ti mer can generate an interrupt request. all requests are combined to a co mmon node request. figure 9 rtc block diagram note: the registers associated with the rtc are not affected by a reset in order to maintain the correct system time even when intermed iate resets are executed. cnt-register rel-register 10 bits 6 bits 6 bits 10 bits t14 mcb05568 t14-register interrupt sub node rtcint mux 8 pre run cnt int3 cnt int2 cnt int1 cnt int0 f cnt f rt c t14rel 10 bits 6 bits 6 bits 10 bits :
xc167-16 derivatives functional description data sheet 43 v1.2, 2006-03 the rtc module can be used for different purposes: ? system clock to determine the current ti me and date, optionally during idle mode, sleep mode, and power down mode ? cyclic time based interrupt, to provid e a system time tick independent of cpu frequency and other resource s, e.g. to wake up r egularly from idle mode. ? 48-bit timer for long term measurements (maximum timespan is > 100 years). ? alarm interrupt for wake -up on a defined time
xc167-16 derivatives functional description data sheet 44 v1.2, 2006-03 3.10 a/d converter for analog signal measurement, a 10-bit a/d converter with 16 multiplexed input channels and a sample an d hold circuit has been integrated on-chip. it uses the method of successive approximation. the sample ti me (for loading the capacitors) and the conversion time is programmable (in tw o modes) and can thus be adjusted to the external circuitry. the a/d c onverter can also operate in 8-bit conversion mode, where the conversion time is further reduced. overrun error detection/prot ection is provided for the conversion result register (addat): either an interrupt request will be generated w hen the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended in such a case unti l the previous result has been read. for applications which require less analog input channels, the re maining channel inputs can be used as digita l input port pins. the a/d converter of the xc167 supports fo ur different conversion modes. in the standard single channel conv ersion mode, the analog leve l on a specified channel is sampled once and converted to a digital result. in the si ngle channel c ontinuous mode, the analog level on a specif ied channel is re peatedly sampled and converted without software intervention. in th e auto scan mode, the analog levels on a prespecified number of channels are sequentially sa mpled and converted. in the auto scan continuous mode, the prespeci fied channels are repeatedly sampled and converted. in addition, the conversion of a specific channel can be insert ed (injected) into a running sequence without disturbing th is sequence. this is call ed channel injection mode. the peripheral event controller (pec) ma y be used to automatically store the conversion results into a ta ble in memory for later eval uation, without requiring the overhead of entering and ex iting interrupt routines for each data transfer. after each reset and also during normal operation the adc automatically performs calibration cycles. this automatic self-calibration cons tantly adjusts the converter to changing operating conditions (e.g. temperature) and comp ensates process variations. these calibration cycles are part of the conversion cycle, so they do not affect the normal operation of the a/d converter. in order to decouple analog inputs from di gital noise and to avoid input trigger noise those pins used for analog in put can be disconnected from the digital io or input stages under software control. this can be selected for each pin se parately via register p5didis (port 5 digital input disable). the auto-power-down feature of the a/d c onverter minimizes the power consumption when no conversion is in progress.
xc167-16 derivatives functional description data sheet 45 v1.2, 2006-03 3.11 asynchronous/synchronous serial interfaces (asc0/asc1) the asynchronous/synchronous serial inte rfaces asc0/asc1 (usarts) provide serial communication with ot her microcontrollers, processors, terminals or external peripheral components. they are upward compatible with the serial ports of the infineon 8-bit microcontroller familie s and support full-duplex asyn chronous communica tion and half- duplex synchronous communicati on. a dedicated baud rate generator with a fractional divider precisely generates all standard baud rates with out oscillator tuning. for transmission, reception, er ror handling, and bau drate detection 5 separate interrupt vectors are provided. in asynchronous mode, 8- or 9- bit data frames (with optional parity bit) are transmitted or received, preceded by a start bit and terminat ed by one or two stop bits. for multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data pl us wake-up bit mode). irda data transmissions up to 115.2 kbit/s with fixed or programma ble irda pulse width are supported. in synchronous mode, bytes (8 bits) are transmitted or rece ived synchronously to a shift clock which is generated by the asc0/1. the lsb is always shifted first. in both modes, transmission and reception of data is fifo-buffered. an autobaud detection unit allows to de tect asynchronous data frames with its baud rate and mode with automatic initializati on of the baudrate generator and the mode control bits. a number of optional hardware error detection cap abilities has been included to increase the reliability of data transfers. a pa rity bit can automatically be generated on transmission or be checked on reception. framing error det ection allows to recognize data frames with missing stop bits. an overrun error will be generated, if the last character received has not been read out of th e receive buffer register at the time the reception of a new ch aracter is complete. summary of features ? full-duplex asynchronous operating modes ? 8- or 9-bit data frames, lsb first, one or two stop bits, pari ty generation/checking ? baudrate from 2.5 mbit/s to 0.6 bit/s (@ 40 mhz) ? multiprocessor mode for automa tic address/data byte detection ? support for irda data trans mission/reception up to ma x. 115.2 kbit/s (@ 40 mhz) ? loop-back capability ? auto baudrate detection ? half-duplex 8-bit synchronous operating mode at 5 mbit/s to 406.9 bit/s (@ 40 mhz) ? buffered transmitter/receiver with fi fo support (8 entries per direction) ? loop-back option availa ble for testing purposes ? interrupt generation on tr ansmitter buffer empty condi tion, last bit transmitted condition, receive buffer fu ll condition, error condition (frame, par ity, overrun error), start and end of an autobaud detection
xc167-16 derivatives functional description data sheet 46 v1.2, 2006-03 3.12 high speed synchronous serial channels (ssc0/ssc1) the high speed synchronous serial channels ssc0/ssc1 su pport full-duplex and half- duplex synchronous commu nication. it may be co nfigured so it inte rfaces with serially linked peripheral compo nents, full spi functi onality is supported. a dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. for transmi ssion, reception and error handling three separate interrupt vectors are provided. the ssc transmits or receives characters of 2 ? 16 bits leng th synchronously to a shift clock which can be generated by the ssc (mast er mode) or by an ex ternal master (slave mode). the ssc can star t shifting with the lsb or with the msb and allows the selection of shifting and latching clock edges as well as the clock polarity. a number of optional hardware error detection cap abilities has been included to increase the reliability of data transfers. transmit error and receive error supervise the correct handling of the data buffer. phase error and baudrate error detect incorrect serial data. summary of features ? master or slave mode operation ? full-duplex or half-duplex transfers ? baudrate generation from 20 mb it/s to 305.18 bit/s (@ 40 mhz) ? flexible data format ? programmable number of data bits: 2 to 16 bits ? programmable shift directio n: lsb-first or msb-first ? programmable clock polarity: idle low or idle high ? programmable clock/data ph ase: data shift with lead ing or trailing clock edge ? loop back option availabl e for testing purposes ? interrupt generation on transmitter bu ffer empty condition, receive buffer full condition, error condition (receive, phase, baudrate, transmit error) ? three pin interface with fl exible ssc pin configuration
xc167-16 derivatives functional description data sheet 47 v1.2, 2006-03 3.13 twincan module the integrated twincan module handles th e completely autonomous transmission and reception of can frames in a ccordance with the can specific ation v2.0 part b (active), i.e. the on-chip twincan modu le can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. two full-can nodes share the twincan module ?s resources to op timize the can bus traffic handling and to mini mize the cpu load. the modul e provides up to 32 message objects, which can be assigned to one of the can nodes and can be combined to fifo- structures. each object provides s eparate masks for acceptance filtering. the flexible combination of full-can functi onality and fifo arch itecture reduces the efforts to fulfill the real-time requirements of complex embedded control applications. improved can bus monitoring functionality as well as th e number of message objects permit precise and comfortabl e can bus traffic handling. gateway functionality allows automatic data exchange be tween two separate can bus systems, which reduces cpu lo ad and improves the real ti me behavior of the entire system. the bit timing for both can no des is derived from the mast er clock and is programmable up to a data rate of 1 mbit/s. each can node uses two pins of port 4, port 7, or port 9 to interface to an external bus transceiver. th e interface pins are assigned via software. figure 10 twincan module block diagram twincan m odule kernel mcb05567 txdca rxdca txdcb rxdcb can node a can node b message object buffer clock control f can interrupt control address decoder twincan control port control
xc167-16 derivatives functional description data sheet 48 v1.2, 2006-03 summary of features ? can functionality according to can specification v2.0 b active ? data transfer rate up to 1 mbit/s ? flexible and powerful messa ge transfer control and error handling capabilities ? full-can functionality and basic ca n functionality fo r each message object ? 32 flexible message objects ? assignment to one of the two can nodes ? configuration as transmit object or receive object ? concatenation to a 2-, 4-, 8-, 16-, or 32-message bu ffer with fifo algorithm ? handling of frames with 11-bit or 29-bit identifiers ? individual programmable acceptance mask register for filtering for each object ? monitoring via a frame counter ? configuration for re mote monitoring mode ? up to eight individu ally programmable inte rrupt nodes can be used ? can analyzer mode for bus monitoring is implemented note: when a can node has the interface line s assigned to port 4, the segment address output on port 4 must be limited. cs lines can be used to increase the total amount of addressable external memory. 3.14 iic bus module the integrated iic bus module handles the transmission an d reception of frames over the two-line iic bus in accor dance with the iic bus specification. the iic module can operate in slave mode, in master mode or in multi-master mode. it can receive and transmit data using 7-bit or 10-bit addressing. up to 4 se nd/receive data bytes can be stored in the ex tended buffers. several physical interfaces (p ort pins) can be established under software control. data can be transferre d at speeds up to 400 kbit/s. two interrupt nodes dedicated to the iic module allow effici ent interrupt service and also support operation via pec transfers. note: the port pins associated with the iic in terfaces must be swit ched to open drain mode, as required by the iic specification.
xc167-16 derivatives functional description data sheet 49 v1.2, 2006-03 3.15 watchdog timer the watchdog timer represen ts one of the fail-safe mechanisms which have been implemented to prevent the co ntroller from malfunctioning for longer periods of time. the watchdog timer is always enabled after a reset of th e chip, and can be disabled until the einit instruction ha s been executed (compatible mo de), or it can be disabled and enabled at any time by executing instructions diswdt and enwdt (enhanced mode). thus, the chip?s start-up procedure is always monitored. the software has to be designed to restart the watchd og timer before it overfl ows. if, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an internal hardwa re reset and pulls the rstout pin low in order to allow external hardware comp onents to be reset. the watchdog timer is a 16-bit timer, cl ocked with the system clock divided by 2/4/128/256. the high by te of the watchdog ti mer register can be set to a prespecified reload value (stored in wdtrel) in order to allow further variation of the monitored time interval. each time it is serviced by the application software, the high byte of the watchdog timer is rel oaded and the low byte is cleared. thus, time intervals between 13 s and 419 ms can be m onitored (@ 40 mhz). the default watchdog timer interval after reset is 3.28 ms (@ 40 mhz).
xc167-16 derivatives functional description data sheet 50 v1.2, 2006-03 3.16 clock generation the clock generation unit uses a programma ble on-chip pll with multiple prescalers to generate the clock signals for the xc167 with high flexibilit y. the master clock f mc is the reference clock signal, and is used for twincan and is ou tput to the external system. the cpu clock f cpu and the system clock f sys are derived from the master clock either directly (1:1) or via a 2:1 prescaler ( f sys = f cpu = f mc / 2). see also section 4.4.1 . the on-chip oscillator can drive an external crystal or accepts an external clock signal. the oscillator clock fr equency can be multiplied by th e on-chip pll (by a programmable factor) or can be divided by a programmable prescaler factor. if the bypass mode is used (direct drive or prescaler) the pll ca n deliver an independent clock to monitor the clock sign al generated by the on-chip oscillator. this pll clock is independent from the xtal1 clock. when the expected o scillator clock transitions are missing the oscillator watchdog (owd) acti vates the pll unlock/owd interrupt node and supplies the cpu with an emergency clock, the pll clock signal. under these circumstances the pll will osci llate with its basic frequency. the oscillator watchdog can be disabled by switching the pll o ff. this reduces power consumption, but also no in terrupt request will be gene rated in case of a missing oscillator clock. note: at the end of an external reset (ea = ?0?) the oscillator watchdog may be disabled via hardware by (ext ernally) pulling the rd line low upon a reset, similar to the standard reset configuration. 3.17 parallel ports the xc167 provides up to 103 i/o lines which are organized into nine input/ output ports and one input port. all port lines are bit- addressable, and all in put/output lines are individually (bit-wise) progra mmable as inputs or outputs via direction registers. the i/o ports are true bidirectional ports which are switched to high impedance state when configured as inpu ts. the output drivers of some i/o ports can be configured (pin by pin) for push/pull operation or open -drain operation via control registers. during the internal reset, all port pins are configured as inputs (except for pin rstout ). the edge characteristics (sh ape) and driver characteristi cs (output current) of the port drivers can be selected via registers poconx. the input threshold of some ports is select able (ttl or cmos like), where the special cmos like input threshold reduces noise se nsitivity due to the input hysteresis. the input threshold may be selected individually for each byte of the respective ports. all port lines have programmable alternate input or output func tions associated with them. all port lines that are not used for thes e alternate functions may be used as general purpose io lines.
xc167-16 derivatives functional description data sheet 51 v1.2, 2006-03 table 7 summary of the xc167?s parallel ports port control alternate functions port0 pad drivers address/data lines or data lines 1) 1) for multiplexed bus cycles. port1 pad drivers address lines 2) 2) for demultiplexed bus cycles. capture inputs or compare outputs, serial interface lines port 2 pad drivers, open drain, input threshold capture inputs or compare outputs, timer control signal, fast external interrupt inputs port 3 pad drivers, open drain, input threshold timer control signals, serial interface lines, optional bus cont rol signal bhe /wrh , system clock output clkout (or fout) port 4 pad drivers, open drain, input threshold segment address lines 3) 3) for more than 64 kbytes of external resources. can interface lines 4) 4) can be assigned by software. port 5 ? analog input channels to the a/d converter, timer control signals port 6 open drain, input threshold capture inputs or compare outputs, bus arbitration signals breq , hlda , hold , optional chip select signals port 7 open drain, input threshold capture inputs or compare outputs, can interface lines 4) port 9 pad drivers, open drain, input threshold capture inputs or compare outputs can interface lines 4) , iic bus interface lines 4) port 20 pad drivers, open drain bus control signals rd , wr /wrl , ready, ale, external access enable pin ea , reset indication output rstout
xc167-16 derivatives functional description data sheet 52 v1.2, 2006-03 3.18 power management the xc167 provides several means to control the power it consumes either at a given time or averaged over a certain timespan . three mechanisms can be used (partly in parallel): ? power saving modes switch the xc167 in to a special operatin g mode (control via instructions). idle mode stops the cpu while the peripherals ca n continue to operate. sleep mode and power down mo de stop all clock signals a nd all operation (rtc may optionally continue running) . sleep mode can be termina ted by external interrupt signals. ? clock generation management controls the distribu tion and the frequency of internal and external clock signals. while th e clock signals for currently inactive parts of logic are disabled auto matically, the user can redu ce the xc167?s cpu clock frequency which drastically reduces the consumed power. external circuitry can be controlled via the programmable frequency output fout. ? peripheral management permits temporary disabling of peripheral modules (control via register syscon3). ea ch peripheral can separat ely be disabled/enabled. the on-chip rtc supports in termittent operation of th e xc167 by generating cyclic wake-up signals. this offers full performance to quickly re act on action requests while the intermittent sleep phases greatly reduce the average power consumption of the system.
xc167-16 derivatives functional description data sheet 53 v1.2, 2006-03 3.19 instruction set summary table 8 lists the instructions of the xc167 in a condensed way. the various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional exec ution of instructio ns, and the opcodes for each instruction can be found in the ?instruction set manual? . this document also provides a deta iled description of each instruction. table 8 instruction set summary mnemonic description bytes add(b) add word (byt e) operands 2 / 4 addc(b) add word (byte) operands with carry 2 / 4 sub(b) subtract word (byte) operands 2 / 4 subc(b) subtract word (byte) operands with carry 2 / 4 mul(u) (un)signed multiply di rect gpr by direct gpr (16- 16-bit) 2 div(u) (un)signed divide register mdl by direct gpr (16-/16-bit) 2 divl(u) (un)signed long divide reg. md by dire ct gpr (32-/16-bit) 2 cpl(b) complement direct word (byte) gpr 2 neg(b) negate direct word (byte) gpr 2 and(b) bitwise an d, (word/byte operands) 2 / 4 (x)or(b) bitwise (exclusive) or , (word/byte operands) 2 / 4 bclr/bset clear/set direct bit 2 bmov(n) move (negated) dire ct bit to direct bit 4 band/bor/bxor and/or/xor dire ct bit with direct bit 4 bcmp compare direct bit to direct bit 4 bfldh/bfldl bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data 4 cmp(b) compare word (byte) operands 2 / 4 cmpd1/2 compare word data to gpr and decrement gpr by 1/2 2 / 4 cmpi1/2 compare word data to gpr and increment gpr by 1/2 2 / 4 prior determine number of shif t cycles to normalize direct word gpr and store result in direct word gpr 2 shl/shr shift left/right direct word gpr 2 rol/ror rotate left/rig ht direct word gpr 2
xc167-16 derivatives functional description data sheet 54 v1.2, 2006-03 ashr arithmetic (sign bit) sh ift right direct word gpr 2 mov(b) move word (byte) data 2 / 4 movbs/z move byte operand to word op. with si gn/zero extension 2 / 4 jmpa/i/r jump absolute/indirect/r elative if condition is met 4 jmps jump absolute to a code segment 4 jb(c) jump relative if direct bit is set (and clear bit) 4 jnb(s) jump relative if direct bit is not set (and set bit) 4 calla/i/r call absolute/indirect/relat ive subroutine if condition is met 4 calls call absolute subroutin e in any code segment 4 pcall push direct word regist er onto system stack and call absolute subroutine 4 trap call interrupt service rout ine via immediate trap number 2 push/pop push/pop direct word register onto/from system stack 2 scxt push direct word register onto system stack and update register with word operand 4 ret(p) return from intra-segment subroutine (and pop direct word register from system stack) 2 rets return from inter-segment subroutine 2 reti return from interr upt service subroutine 2 sbrk software break 2 srst software reset 4 idle enter idle mode 4 pwrdn enter power down mode (supposes nmi -pin being low) 4 srvwdt service watchdog timer 4 diswdt/enwdt disable/e nable watchdog timer 4 einit signify end-of-initialization on rstout pin 4 atomic begin atomic sequence 2 extr begin extended register sequence 2 extp(r) begin extended page (and register) sequence 2 / 4 exts(r) begin extended segment ( and register) sequence 2 / 4 nop null operation 2 table 8 instruction set summary (cont?d) mnemonic description bytes
xc167-16 derivatives functional description data sheet 55 v1.2, 2006-03 comul/comac multiply (and accumulate) 4 coadd/cosub add/subtract 4 co(a)shr/coshl (arithmetic) shift right/shift left 4 coload/store load accumula tor/store mac register 4 cocmp/max/min compare (maximum/minimum) 4 coabs/cornd absolute val ue/round accumulator 4 comov/neg/nop data move/negate accumulator/null operation 4 table 8 instruction set summary (cont?d) mnemonic description bytes
xc167-16 derivatives electrical parameters data sheet 56 v1.2, 2006-03 4 electrical parameters 4.1 general parameters note: stresses above those listed under ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions abov e those indicated in the operational sections of this specification is not im plied. exposure to absolute maximum rating conditions for extended periods ma y affect device reliability. during absolute maximum ra ting overload conditions ( v in > v ddp or v in < v ss ) the voltage on v ddp pins with respect to ground ( v ss ) must not exceed the values defined by the absol ute maximum ratings. table 9 absolute maximum ratings parameter symbol limit values unit notes min. max. storage temperature t st -65 150 c 1) 1) moisture sensitivity level (msl) 3, conforming to jedec j-std-020c for 240 c. junction temperature t j -40 150 c under bias voltage on v ddi pins with respect to ground ( v ss ) v ddi -0.5 3.25 v ? voltage on v ddp pins with respect to ground ( v ss ) v ddp -0.5 6.2 v ? voltage on any pin with respect to ground ( v ss ) v in -0.5 v ddp + 0.5 v? input current on any pin during overload condition ?-1010ma? absolute sum of all input currents during overload condition ? ? |100| ma ?
xc167-16 derivatives electrical parameters data sheet 57 v1.2, 2006-03 operating conditions the following operating condit ions must not be exceeded to ensure correct operation of the xc167. all parameters spec ified in the following sectio ns refer to these operating conditions, unless otherwise noticed. table 10 operating condition parameters parameter symbol limit values unit notes min. max. digital supply voltage for the core v ddi 2.35 2.7 v active mode, f cpu = f cpumax 1)2) 1) f cpumax = 40 mhz for devices marked ? 40f, f cpumax = 20 mhz for devices marked ? 20f. 2) external circuitry must guarantee low level at the rstin pin at least until both power supply voltages have reached their operating range. digital supply voltage for io pads v ddp 4.4 5.5 v active mode 2) supply voltage difference ? v dd -0.5 ? v v ddp - v ddi 3) 3) this limitation must be fulfilled under all operating conditions including power-ramp-up, power-ramp-down, and power-save modes. digital ground voltage v ss 0 v reference voltage overload current i ov -5 5 ma per io pin 4)5) 4) overload conditions occur if the standard operating condit ions are exceeded, i.e. the voltage on any pin exceeds the specified range: v ov > v ddp + 0.5 v ( i ov > 0) or v ov < v ss - 0.5 v ( i ov < 0). the absolute sum of input overload currents on all pins may not exceed 50 ma . the supply voltages must remain within the specified limits. proper operation is not guaranteed if overload cond itions occur on functional pins such as xtal1, rd , wr , etc. 5) not subject to production test - verified by design/characterization. -2 5 ma per analog input pin 4)5) overload current coupling factor for analog inputs 6) k ova ?1.0 10 -4 ? i ov > 0 ?1.5 10 -3 ? i ov < 0 overload current coupling factor for digital i/o pins 6) k ovd ?5.0 10 -3 ? i ov > 0 ?1.0 10 -2 ? i ov < 0 absolute sum of overload currents | i ov |? 50 ma 5) external load capacitance c l ? 50 pf pin drivers in default mode 7) ambient temperature t a ?? c see table 1
xc167-16 derivatives electrical parameters data sheet 58 v1.2, 2006-03 parameter interpretation the parameters listed in the following partly repr esent the characteri stics of the xc167 and partly its demand s on the system. to aid in interp reting the parameters right, when evaluating them for a design, they are marked in column ?symbol?: cc ( c ontroller c haracteristics): the logic of the xc167 will provide sig nals with the respecti ve characteristics. sr ( s ystem r equirement): the external system must prov ide signals with the respecti ve characteristics to the xc167. 6) an overload current ( i ov ) through a pin injects a certain error current ( i inj ) into the adjacent pins. this error current adds to the respective pin?s leakage current ( i oz ). the amount of error current depends on the overload current and is defined by the overload coupling factor k ov . the polarity of the injected error current is inverse compared to the polarity of the overload current that produces it. the total current through a pin is | i tot | = | i oz | + (| i ov | k ov ). the additional error cu rrent may distort the input voltage on analog inputs. 7) the timing is valid for pin drivers operating in defaul t current mode (selected after reset). reducing the output current may lead to increased delays or reduced driving capability ( c l ).
xc167-16 derivatives electrical parameters data sheet 59 v1.2, 2006-03 4.2 dc parameters table 11 dc characteristics (operating conditions apply) 1) parameter symbol limit va lues unit test condition min. max. input low voltage ttl (all except xtal1, xtal3) v il sr -0.5 0.2 v ddp - 0.1 v? input low voltage for xtal1, xtal3 2) v ilc sr -0.5 0.3 v ddi v? input low voltage (special threshold) v ils sr -0.5 0.45 v ddp v 3) input high voltage ttl (all except xtal1, xtal3) v ih sr 0.2 v ddp + 0.9 v ddp + 0.5 v ? input high voltage xtal1, xtal3 2) v ihc sr 0.7 v ddi v ddi + 0.5 v ? input high voltage (special threshold) v ihs sr 0.8 v ddp - 0.2 v ddp + 0.5 v 3) input hysteresis (special threshold) hys 0.04 v ddp ?v v ddp in [v], series resis- tance = 0 ? 3) output low voltage v ol cc ? 1.0 v i ol i olmax 4) ?0.45v i ol i olnom 4)5) output high voltage 6) v oh cc v ddp - 1.0 ? v i oh i ohmax 4) v ddp - 0.45 ?v i oh i ohnom 4)5) input leakage current (port 5) 7) i oz1 cc ? 300 na 0 v < v in < v ddp , t a 125 c 200 na 0 v < v in < v ddp , t a 85 c 14) input leakage current (all other 8) ) 7) i oz2 cc ? 500 na 0.45 v < v in < v ddp configuration pull-up current 9) i cpuh 10) ?-10 a v in = v ihmin i cpul 11) -100 ? a v in = v ilmax
xc167-16 derivatives electrical parameters data sheet 60 v1.2, 2006-03 configuration pull- down current 12) i cpdl 10) ?10 a v in = v ilmax i cpdh 11) 120 ? a v in = v ihmin level inactive hold current 13) i lhi 10) ?-10 a v out = 0.5 v ddp level active hold current 13) i lha 11) -100 ? a v out = 0.45 v xtal1, xtal3 input current i il cc ? 20 a0 v < v in < v ddi pin capacitance 14) (digital i nputs/outputs) c io cc ? 10 pf ? 1) keeping signal levels within the limi ts specified in this table, ensures operation without overload conditions. for signal levels outside these specifications, also refer to the specification of the overload current i ov . 2) if xtal3 is driven by a crystal, reaching an amplitude (peak to peak) of 0.25 v ddi is sufficient. 3) this parameter is tested for p2, p3, p4, p6, p7, p9. 4) the maximum deliverable output curr ent of a port driver depends on th e selected output driver mode, see table 12 , current limits for port output drivers . the limit for pin groups must be respected. 5) as a rule, with decreasing output current the out put levels approach the respective supply level ( v ol v ss , v oh v ddp ). however, only the levels for nom inal output curr ents are guaranteed. 6) this specification is not valid for outputs which are sw itched to open drain mode. in this case the respective output will float and the voltage re sults from the external circuitry. 7) an additional error current ( i inj ) will flow if an overload current flows through an adjacent pi n. please refer to the definition of the overload coupling factor k ov . 8) the driver of p3.15 is designed for faster switching, because this pin can deliver the reference clock for the bus interface (clkout). the maximum leakage cu rrent for p3.15 is, ther efore, increased to 1 a. 9) this specification is valid during reset for configuration on rd , wr , ea , port0. the pull-ups on rd and wr (wrl /wrh ) are also active during bus hold. 10) the maximum current may be drawn while the respective signal line remains inactive. 11) the minimum current must be drawn to drive the respective signal line active. 12) this specification is valid dur ing reset for configuration on ale. the pull-down on ale is also active during bus hold. 13) this specification is valid during reset for pins p6.4-0, which can act as cs outputs. the pull-ups on cs outputs are also active during bus hold. the pull-up on pin hlda is active when arbitration is enabled and the ebc operates in slave mode. 14) not subject to production test - verified by design/characterization. table 11 dc characteristics (operating conditions apply) 1) (cont?d) parameter symbol limit va lues unit test condition min. max.
xc167-16 derivatives electrical parameters data sheet 61 v1.2, 2006-03 table 12 current limits fo r port output drivers port output driver mode maximum output current ( i olmax , - i ohmax ) 1) 1) an output current above | i oxnom | may be drawn from up to three pins at the same time. for any group of 16 neighboring port output pi ns the total output current in each direction ( i ol and - i oh ) must remain below 50 ma. nominal output current ( i olnom , - i ohnom ) strong driver 10 ma 2.5 ma medium driver 4.0 ma 1.0 ma weak driver 0.5 ma 0.1 ma table 13 power consumption xc167 (operating conditions apply) parameter sym- bol limit values unit test condition min. max. power supply current (active) with all peripherals active i ddi ? 15 + 2.6 f cpu ma f cpu in [mhz] 1)2) 1) during flash programming or er ase operations the supply curr ent is increased by max. 5 ma. 2) the supply current is a function of the operat ing frequency. this dependency is illustrated in figure 11 . these parameters are tested at v ddimax and maximum cpu clock frequency with all outputs disconnected and all inputs at v il or v ih . pad supply current i ddp ?5 ma 3) 3) the pad supply voltage pins ( v ddp ) mainly provides the current consumed by the pin output drivers. a small amount of current is consumed even though no output s are driven, because the drivers? input stages are switched and also the flash module draws some power from the v ddp supply. idle mode supply current with all peripherals active i idx ? 15 + 1.2 f cpu ma f cpu in [mhz] 2) sleep and po wer down mode supply current caused by leakage 4) i pdl 5) ? 128,000 e - ma v ddi = v ddimax 6) t j in [ c] = 4670 / (273 + t j ) sleep and po wer down mode supply current caused by leakage and the rtc running, clocked by the main oscillator 4) i pdm 7) ? 0.6 + 0.02 f osc + i pdl ma v ddi = v ddimax f osc in [mhz] sleep and po wer down mode supply current caused by leakage and the rtc running, clocked by the auxiliary oscillator at 32 khz 4) i pda ? 0.1 + i pdl ma v ddi = v ddimax
xc167-16 derivatives electrical parameters data sheet 62 v1.2, 2006-03 4) the total supply current in sleep and power down mode is the sum of the temperature dependent leakage current and the frequenc y dependent current for rtc a nd main oscillator or auxili ary oscillator (if active). 5) this parameter is determined mainly by the transistor leakage currents. this current heavily depends on the junction temperature (see figure 13 ). the junction temperature t j is the same as the ambient temperature t a if no current flows through the port output drivers. otherwise, the result ing temperature difference must be taken into account. 6) all inputs (including pins configured as inputs) at 0 v to 0.1 v or at v ddp - 0.1 v to v ddp , all outputs (including pins configured as outputs) disconnecte d. this parameter is tested at 25 c and is valid for t j 25 c. 7) this parameter is determi ned mainly by the current c onsumed by the oscillator swit ched to low gain mode (see figure 12 ). this current, however, is influenced by the external oscillato r circuitry (crystal, capacitors). the given values refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry.
xc167-16 derivatives electrical parameters data sheet 63 v1.2, 2006-03 figure 11 supply/idle current as a function of operating frequency i [ma] f cpu [mhz] 10 20 30 40 i ddimax i ddityp i idxmax i idxtyp 20 40 60 80 100 120 140
xc167-16 derivatives electrical parameters data sheet 64 v1.2, 2006-03 figure 12 sleep and power down supply current due to rtc and oscillator running, as a function of oscillator frequency figure 13 sleep and power down leak age supply current as a function of temperature i [ma] f osc [mhz] 4 8 12 16 i pdmmax i pdmtyp 1.0 2.0 3.0 i pdamax 0.1 32 khz [ma] t j [ c] 0 50 100 150 i pdo 0.5 1.0 1.5 -50
xc167-16 derivatives electrical parameters data sheet 65 v1.2, 2006-03 4.3 analog/digital converter parameters table 14 a/d converter characteristics (operating conditions apply) parameter symbol limit values unit test condition min. max. analog reference supply v aref sr 4.5 v ddp + 0.1 v 1) 1) tue is tested at v aref = v ddp + 0.1 v, v agnd = 0 v. it is verified by design for all other voltages within the defined voltage range. if the analog reference supply vo ltage drops below 4.5 v (i.e. v aref 4.0 v) or exceeds the power supply voltage by up to 0.2 v (i.e. v aref = v ddp + 0.2 v) the maximum tue is increased to 3 lsb. this range is not subject to production test. the specified tue is guaranteed only, if the absolute sum of input overload currents on port 5 pins (see i ov specification) does not exceed 10 ma, and if v aref and v agnd remain stable during the respective period of time. during the reset calibration sequence the maximum tue may be 4 lsb. analog reference ground v agnd sr v ss - 0.1 v ss + 0.1 v ? analog input voltage range v ain sr v agnd v aref v 2) 2) v ain may exceed v agnd or v aref up to the absolute maximum ratings. however, the conversion result in these cases will be x000 h or x3ff h , respectively. basic clock frequency f bc 0.5 20 mhz 3) conversion time for 10-bit result 4) t c10p cc 52 t bc + t s + 6 t sys ? post-calibr. on t c10 cc 40 t bc + t s + 6 t sys ? post-calibr. off conversion time for 8-bit result 4) t c8p cc 44 t bc + t s + 6 t sys ? post-calibr. on t c8 cc 32 t bc + t s + 6 t sys ? post-calibr. off calibration time after reset t cal cc 484 11,696 t bc 5) total unadjusted error tue cc ? 2lsb 1) total capacitance of an analog input c aint cc ? 15 pf 6) switched capacitance of an analog input c ains cc ? 10 pf 6) resistance of the analog input path r ain cc ? 2 k ? 6) total capacitance of the reference input c areft cc ? 20 pf 6) switched capacitance of the reference input c arefs cc ? 15 pf 6) resistance of the reference input path r aref cc ? 1 k ? 6)
xc167-16 derivatives electrical parameters data sheet 66 v1.2, 2006-03 figure 14 equivalent circ uitry for analog inputs 3) the limit values for f bc must not be exceeded when selecting the peripheral frequency and the adctc setting. 4) this parameter includes the sample time t s , the time for determining the digital result and the time to load the result register with the conversion result ( t sys = 1/ f sys ). values for the basic clock t bc depend on programming and can be taken from table 15 . when the post-calibration is switched off, the conversion time is reduced by 12 t bc . 5) the actual duration of the reset calibration depen ds on the noise on the reference signal. conversions executed during the reset calibration increase the calibration time. the tue for those conversions may be increased. 6) not subject to production test - verified by design/characterization. the given parameter values cover the complete o perating range. under relaxed operating conditions (temperature, supply voltage) reduced values can be us ed for calculations. at room temperature and nominal supply voltage the following typical values can be used: c ainttyp = 12 pf, c ainstyp = 7 pf, r aintyp = 1.5 k ? , c arefttyp = 15 pf, c arefstyp = 13 pf, r areftyp = 0.7 k ? . a/d converter mcs05570 r source v ain c ext c aint c ains - r ain, on c ains
xc167-16 derivatives electrical parameters data sheet 67 v1.2, 2006-03 sample time and conversion time of the xc167?s a/d co nverter are programmable. in compatibility mode, the above ti ming can be calculated using table 15 . the limit values for f bc must not be exceeded when selecting adctc. converter timing example: table 15 a/d converter computation table 1) 1) these selections are available in compatibility mode. an improved mechanism to control the adc input clock can be selected. adcon.15|14 (adctc) a/d converter basic clock f bc adcon.13|12 (adstc) sample time t s 00 f sys / 4 00 t bc 8 01 f sys / 2 01 t bc 16 10 f sys / 16 10 t bc 32 11 f sys / 8 11 t bc 64 assumptions: f sys = 40 mhz (i.e. t sys = 25 ns), adctc = ?01?, adstc = ?00? basic clock f bc = f sys / 2 = 20 mhz, i.e. t bc = 50 ns sample time t s = t bc 8 = 400 ns conversion 10-bit: with post-calibr. t c10p = 52 t bc + t s + 6 t sys = (2600 + 400 + 150) ns = 3.15 s post-calibr. off t c10 = 40 t bc + t s + 6 t sys = (2000 + 400 + 150) ns = 2.55 s conversion 8-bit: with post-calibr. t c8p = 44 t bc + t s + 6 t sys = (2200 + 400 + 150) ns = 2.75 s post-calibr. off t c8 = 32 t bc + t s + 6 t sys = (1600 + 400 + 150) ns = 2.15 s
xc167-16 derivatives electrical parameters data sheet 68 v1.2, 2006-03 4.4 ac parameters 4.4.1 definition of internal timing the internal operation of th e xc167 is controlled by the internal master clock f mc . the master clock signal f mc can be generated from t he oscillator clock signal f osc via different mechanisms. the duration of master clock periods (tcms) and their variation (and also the derived external timing) depend on th e used mechanism to generate f mc . this influence must be regarded when calculating the timings for the xc167. figure 15 generation mechanis ms for the master clock note: the example for pll operation shown in figure 15 refers to a pll factor of 1:4, the example for prescaler operation refers to a divider factor of 2:1. the used mechanism to generat e the master clock is sele cted by register pllcon. cpu and ebc are clocked wi th the cpu clock signal f cpu . the cpu clock can have the same frequency as the master clock ( f cpu = f mc ) or can be the master clock divided by two: f cpu = f mc / 2. this factor is selected by bit cpsy s in register syscon1. mct05555 phase locked loop operation (1:n) f osc direct clock drive (1:1) prescaler operation (n:1) f mc f osc f mc f osc f mc tcm tcm tcm
xc167-16 derivatives electrical parameters data sheet 69 v1.2, 2006-03 the specification of the extern al timing (ac charac teristics) depends on the period of the cpu clock, called ?tcp?. the other peripherals are supplied with th e system clock signal f sys which has the same frequency as the cpu clock signal f cpu . bypass operation when bypass operation is co nfigured (pllctrl = 0x b ) the master cloc k is derived from the internal oscillator (in put clock signal xtal1) thro ugh the input- and output- prescalers: f mc = f osc / ((pllidiv+1) (pllodiv+1)). if both divider factors are selected as ?1? (pllidiv = pllodiv = ?0?) the frequency of f mc directly follows the frequency of f osc so the high and low time of f mc is defined by the duty cycle of the input clock f osc . the lowest master clock frequency is achiev ed by selecting the ma ximum values for both divider factors: f mc = f osc / ((3 + 1) (14 + 1)) = f osc / 60. phase locked loop (pll) when pll operation is c onfigured (pllctrl = 11 b ) the on-chip phase locked loop is enabled and provides the mast er clock. the pll multiplies the input frequency by the factor f ( f mc = f osc f ) which results from the input divi der, the multiplication factor, and the output divider ( f = pllmul+1 / (pllidiv+1 pllodiv+1)). the pll circuit synchronizes the master clock to the input clock. this sync hronization is done smoothly, i.e. the master clock frequenc y does not change abruptly. due to this adaptation to t he input clock th e frequency of f mc is constantly adjusted so it is locked to f osc . the slight variati on causes a jitter of f mc which also affects the duration of individual tcms. the timing listed in t he ac characteristics re fers to tcps. because f cpu is derived from f mc , the timing must be calculated using th e minimum tcp possible under the respective circumstances. the actual minimum value for tcp depends on the jitter of the pll. as the pll is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the rela tive deviation for periods of mo re than one tcp is lower than for one single tcp (see formula and figure 16 ). this is especially important fo r bus cycles using waitstates and e.g. for the operation of timers, serial interfac es, etc. for all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the pll jitter is negligible.
xc167-16 derivatives electrical parameters data sheet 70 v1.2, 2006-03 the value of the accumulat ed pll jitter depends on the number of consecutive vco output cycles within the respec tive timeframe. the vco outp ut clock is divided by the output prescaler (k = pl lodiv+1) to generate th e master clock signal f mc . therefore, the number of vco cycles can be represented as k n , where n is the number of consecutive f mc cycles (tcm). for a period of n tcm the accumulated pll jitter is defined by the deviation d n : d n [ns] = (1.5 + 6.32 n / f mc ); f mc in [mhz], n = number of consecutive tcms. so, for a period of 3 tcms @ 20 mhz and k = 12: d 3 = (1.5 + 6.32 3 / 20) = 2.448 ns. this formula is applicable for k n < 95. for longer periods the k n = 95 value can be used. this steady value c an be approximated by: d nmax [ns] = (1.5 + 600 / (k f mc )). figure 16 approximated accumulated pll jitter note: the bold lines indicate the minimum accumulated jitter which can be achieved by selecting the maximum possible output prescaler factor k. different frequency band s can be selected for the vco, so the operati on of the pll can be adjusted to a wide range of input and output frequencies: mcd05566 n 0 1 2 3 4 5 6 7 8 acc. jitter d n 0510 15 20 25 ns k = 15 k = 12 k = 10 k = 8 k = 6 k = 5 1 10 mhz 20 mhz 40 mhz
xc167-16 derivatives electrical parameters data sheet 71 v1.2, 2006-03 table 16 vco bands for pll operation 1) 1) not subject to production test - verified by design/characterization. pllcon.pllvb vco frequency range base frequency range 00 100 ? 150 mhz 20 ? 80 mhz 01 150 ? 200 mhz 40 ? 130 mhz 10 200 ? 250 mhz 60 ? 180 mhz 11 reserved
xc167-16 derivatives electrical parameters data sheet 72 v1.2, 2006-03 4.4.2 on-chip flash operation the xc167?s flash module delivers da ta within a fix ed access time (see table 17 ). accesses to the flash module are controlled by the pmi and take 1+ws clock cycles, where ws is the number of flash access waitstates sele cted via bitfield wsflash in register imbctrl. th e resulting duration of the ac cess phase must cover the access time t acc of the flash array. ther efore, the required flash waitstates depend on the actual system frequency. note: the flash access wait states only affect non- sequential accesses. due to prefetching mechanisms, th e performance for sequenti al accesses (depending on the software structure) is only pa rtially influenced by waitstates. in typical applications, eliminating one waitstate incr eases the average performance by 5% ? 15%. example: for an operating frequency of 40 mhz (clock cycle = 25 ns), devices can be operated with 1 waitstate: ((1+1) 25 ns) 50 ns. table 18 indicates the interrelation of waitstates and system frequency. note: the maximum achievable system frequency is limited by the properties of the respective derivative, i.e. 40 mhz (or 20 mhz fo r xxx-16f20f devices). table 17 flash characteristics (operating conditions apply) parameter symbol limit values unit min. typ. max. flash module access time t acc cc ? ? 50 ns programming time per 128-byte block t pr cc ? 2 1) 1) programming and erase time depends on the syste m frequency. typical values are valid for 40 mhz. 5ms erase time per sector t er cc ? 200 1) 500 ms table 18 flash access waitstates required waitstates fr equency range for 0 ws (wsflash = 00 b ) f cpu 20 mhz 1 ws (wsflash = 01 b ) f cpu 40 mhz
xc167-16 derivatives electrical parameters data sheet 73 v1.2, 2006-03 4.4.3 external clock drive xtal1 figure 17 external clock drive xtal1 note: if the on-chip oscillator is used together wi th a crystal or a ce ramic resonator, the oscillator frequency is limited to a range of 4 mhz to 16 mhz. it is strongly recommended to measur e the oscillation al lowance (negative resistance) in the final target system (layout) to de termine the optimum parameters for the oscillator operation. pl ease refer to the lim its specified by the crystal supplier. when driven by an external clock signa l it will accept the specified frequency range. operation at lower input frequencies is possible but is verified by design only (not subject to production test). table 19 external clock drive characteristics (operating conditions apply) parameter symbol limit values unit min. max. oscillator period t osc sr 25 250 1) 1) the maximum limit is only relevant for pll operation to ensure the minimum input frequency for the pll. ns high time 2) 2) the clock input signal must reach the defined levels v ilc and v ihc . t 1 sr 6 ? ns low time 2) t 2 sr 6 ? ns rise time 2) t 3 sr ? 8 ns fall time 2) t 4 sr ? 8 ns mct05572 t 1 t 2 t osc t 3 t 4 0.5 v ddi v ilc v ihc
xc167-16 derivatives electrical parameters data sheet 74 v1.2, 2006-03 4.4.4 testing waveforms figure 18 input output waveforms figure 19 float waveforms mcd05556 0.45 v 0.8 v 2.0 v input signal (driven by tester) output signal (measured) hold time output delay output delay hold time output timings refer to the rising edge of clkout. input timings are calculat ed from the time , when the inpu t signal reaches v ih or v il , respectively. mca05565 timing reference points v load + 0.1 v v load - 0.1 v v oh - 0.1 v v ol + 0.1 v for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, but begins to fl oat when a 100 mv change from the loaded v oh / v ol level occurs ( i oh / i ol = 20 ma).
xc167-16 derivatives electrical parameters data sheet 75 v1.2, 2006-03 4.4.5 external bus timing figure 20 clkout signal timing table 20 clkout reference signal parameter symbol limits unit min. max. clkout cycle time tc 5 cc 40/30/25 1) 1) the clkout cycle time is influenced by the pll jitter (given values apply to f cpu = 25/33/40 mhz). for longer periods the relative deviation decreases (see pll deviation formula). ns clkout high time tc 6 cc8?ns clkout low time tc 7 cc6?ns clkout rise time tc 8 cc?4ns clkout fall time tc 9 cc?4ns mct05571 clkout t c5 t c6 t c7 t c8 t c9
xc167-16 derivatives electrical parameters data sheet 76 v1.2, 2006-03 variable memory cycles external bus cycles of the xc167 are executed in five subsequent cycle phases (ab, c, d, e, f). the duration of each cycle phase is prog rammable (via the tconcsx registers) to adapt th e external bus cycles to the resp ective external module (memory, peripheral, etc.). the duration of the access phase can optionally be controlled by the external module via the ready handshake input. this table provides a summary of the phases and the re spective choices for their duration. note: the bandwidth of a pa rameter (minimum and maximum value) covers the whole operating range (temperature , voltage) as well as pr ocess variations. within a given device, however, this bandwidth is smaller than the specified range. this is also due to interdependen cies between certain param eters. some of these interdependencies are de scribed in additional no tes (see standard timing). table 21 programmable bus cycle phases (see timing diagrams) bus cycle phase parameter valid values unit address setup phase, the standard du ration of this phase (1 ? 2 tcp) can be extended by 0 ? 3 tcp if the address window is changed tp ab 1 ? 2 (5) tcp command delay phase tp c 0 ? 3 tcp write data setup/mux tristate phase tp d 0 ? 1 tcp access phase tp e 1 ? 32 tcp address/write da ta hold phase tp f 0 ? 3 tcp
xc167-16 derivatives electrical parameters data sheet 77 v1.2, 2006-03 note: the shaded paramet ers have been verified by characterization. they are not subject to production test. table 22 external bus cycle timing (operating conditions apply) parameter symbol limits unit min. max. output valid delay for: rd , wr (l /h ) tc 10 cc 113ns output valid delay for: bhe , ale tc 11 cc -1 7 ns output valid delay for: a23 ? a16, a15 ? a0 (on port1) tc 12 cc 116ns output valid delay for: a15 ? a0 (on port0) tc 13 cc 316ns output valid delay for: cs tc 14 cc 114ns output valid delay for: d15 ? d0 (write data, mux-mode) tc 15 cc 317ns output valid delay for: d15 ? d0 (write data, demux-mode) tc 16 cc 317ns output hold time for: rd , wr (l /h ) tc 20 cc -3 3ns output hold time for: bhe , ale tc 21 cc 0 8ns output hold time for: a23 ? a16, a15 ? a0 (on port0) tc 23 cc 1 13 ns output hold time for: cs tc 24 cc -3 3ns output hold time for: d15 ? d0 (write data) tc 25 cc 1 13 ns input setup time for: ready, d15 ? d0 (read data) tc 30 sr 24 ? ns input hold time ready, d15 ? d0 (read data) 1) 1) read data are latched with the same (internal) clock e dge that triggers the address change and the rising edge of rd . therefore address changes before the end of rd have no impact on (demultiplexed) read cycles. read data can be removed after the rising edge of rd . tc 31 sr -5 ? ns
xc167-16 derivatives electrical parameters data sheet 78 v1.2, 2006-03 figure 21 multiplexed bus cycle clkout tp ab tp c tp d tp e tp f ale tc 21 tc 11 a23-a16, bhe, csx tc 11 / tc 14 rd wr(l/h) tc 20 tc 10 data in ad15-ad0 (read) tc 30 tc 31 mct05557 ad15-ad0 (write) tc 13 tc 15 tc 25 tc 13 tc 23 data out low address high address low address
xc167-16 derivatives electrical parameters data sheet 79 v1.2, 2006-03 figure 22 demultiplexed bus cycle address tp ab tp c tp d tp e tp f tc 21 tc 11 tc 11 / tc 14 tc 20 tc 10 data in tc 30 tc 31 mct05558 tc 16 tc 25 clkout ale a23-a0, bhe, csx rd wr(l/h) d15-d0 (read) d15-d0 (write) data out
xc167-16 derivatives electrical parameters data sheet 80 v1.2, 2006-03 bus cycle control via ready input the duration of an external bus cycle can be c ontrolled by the extern al circuitry via the ready input signal. the po larity of this input si gnal can be selected. synchronous ready permits the shortest possibl e bus cycle but requires the input signal to be synchronous to the reference signal clkout. asynchronous ready puts no timing constraints on the input signal but incurs one waitstate minimum due to the additional synchronization stage. the minimum duration of an asynchronous read y signal to be safely synch ronized must be one clkout period plus the i nput setup time. an active ready signal can be deactivated in response to the trailing (r ising) edge of the corresponding command (rd or wr ). if the next followi ng bus cycle is ready- controlled, an active ready signal must be disabled before the fi rst valid sample poin t for the next bus cycle. this sample point depends on the prog rammed phases of the next following cycle.
xc167-16 derivatives electrical parameters data sheet 81 v1.2, 2006-03 figure 23 ready timing note: if the ready input is samp led inactive at the indicate d sampling point (?not rdy?) a ready-controlled waitstate is inserted ( tp rdy ), sampling the ready input active at the indicated sampling point (?ready?) terminates the currently running bus cycle. note the different sampli ng points for synchronous and asynchronous ready. this example uses one mandatory waitstate (see tp e ) before the ready input is evaluated. mct05559 ready asynchron. not rdy ready data out tc 25 tc 30 d15-d0 (write) ready synchronous not rdy ready data in d15-d0 (read) tc 10 rd, wr tp d tp e tp rdy tp f clkout tc 20 tc 30 tc 31 tc 31 tc 30 tc 31 tc 30 tc 31 tc 30 tc 31
xc167-16 derivatives electrical parameters data sheet 82 v1.2, 2006-03 external bus arbitration note: the shaded paramet ers have been verified by characterization. they are not subject to production test. table 23 bus arbitration timing (operating conditions apply) parameter symbol limits unit min. max. input setup time for: hold input tc 40 sr 24 ? ns output delay rising edge for: hlda , breq tc 41 cc 16ns output delay falling edge for: hlda tc 42 cc 110ns
xc167-16 derivatives electrical parameters data sheet 83 v1.2, 2006-03 figure 24 external bus arbitr ation, releasing the bus notes 1. the xc167 will complete the currently running bus cyc le before granting bus access. 2. this is the first possibility for breq to get active. 3. the control outputs will be resistive high ( pull-up) after being driven inactive (ale will be low). mct05560 tc 10 / tc 14 addr, data, bhe csx, rd, wr(l/h) breq tc 40 hold hlda clkout tc 42 2) 3) 1)
xc167-16 derivatives electrical parameters data sheet 84 v1.2, 2006-03 figure 25 external bus arbitr ation, regaining the bus notes 1. this is the last chance for breq to trigger the indi cated regain-sequence. even if breq is activated earlier, the rega in-sequence is in itiated by hold going high. please note that hold may also be deactivated without the xc 167 requesting the bus. 2. the control outputs will be resistive high (pull-up) before being driven inactive (ale will be low). 3. the next xc167 driven bus cycle may start here. mct05561 tc 10 / tc 14 addr, data, bhe csx, rd, wr(l/h) breq tc 40 hold hlda clkout tc 41 3) 1) tc 41 tc 11 / tc 12 / tc 13 / tc 15 / tc 16 2)
xc167-16 derivatives package and reliability data sheet 85 v1.2, 2006-03 5 package and reliability 5.1 packaging package outlines figure 26 p-tqfp-144-19 (plastic thin quad flat package) table 24 package parame ters (p-tqfp-144-19) parameter symbol limit values unit notes min. max. power dissipation p diss ?0.8w? thermal resistance r tha ?32k/wchip-ambient 1) 2) 144x h 4x index marking 144 1 ?.05 a 0.22 0.5 22 20 d 1) 17.5 0.08 2) a-b m d 0.2 0.2 22 b 20 1) a-b a-b d d h ?.05 1.4 144x c c 0.1 ?.05 1.6 max. 0.08 0.6 ?.15 0.12 +0.08 -0.03 7? max. does not include plastic or metal protrusion of 0.25 max. per side does not include dambar protrusion of 0.08 max. per side gpp09243 you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . dimensions in mm
xc167-16 derivatives package and reliability data sheet 86 v1.2, 2006-03 5.2 flash memory parameters the data retention time of t he xc167?s flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of ti mes the flash memory has been erased and programmed. table 25 flash parameters (xc167, 128 kbytes) parameter symbol limit values unit notes min. max. data retention time t ret 15 ? years 10 3 erase/program cycles flash erase endurance n er 20 10 3 ? cycles data retention time 5years
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